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Merge pull request #599 from ucb-bar/dev

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Chipyard 1.4.0 Release
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Jerry Zhao
2021-01-20 15:26:47 -08:00
committed by GitHub
parent cca3cd087c d4f8f56465
commit 58076cfb26
196 changed files with 7922 additions and 3008 deletions
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docs/TileLink-Diplomacy-Reference/Register-Router.rst
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@@ -32,7 +32,7 @@ The default value is 4 bytes. The ``concurrency`` argument is the size of the
internal queue for TileLink requests. By default, this value is 0, which means
there will be no queue. This value must be greater than 0 if you wish to
decoupled requests and responses for register accesses. This is discussed
in :ref:`Using Functions`.
in :ref:`TileLink-Diplomacy-Reference/Register-Router:Using Functions`.
The main way to interact with the node is to call the ``regmap`` method, which
takes a sequence of pairs. The first element of the pair is an offset from the
@@ -128,7 +128,7 @@ Register Routers for Other Protocols
One useful feature of the register router interface is that you can easily
change the protocol being used. For instance, in the first example in
:ref:`Basic Usage`, you could simply change the ``TLRegisterNode`` to
:ref:`TileLink-Diplomacy-Reference/Register-Router:Basic Usage`, you could simply change the ``TLRegisterNode`` to
and ``AXI4RegisterNode``.
.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala