Rocket core vs Rocket Chip

docs/Generators/Rocket.rst

@@ -1,8 +1,9 @@
-Rocket
+Rocket Core
 ====================================
 
-`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar core generator that is supported by `SiFive <https://www.sifive.com/>`__.
-It supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
+`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley an currently supported by `SiFive <https://www.sifive.com/>`__. The Rocket core is used as a component (a `tile`) within the Rocket Chip SoC generator.
+
+The Rocket core supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
 It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
 Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS).
 For floating-point,  Rocket  makes  use  of  Berkeley’s  Chisel  implementations  of  floating-point  units.