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Bump testchipip

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This commit is contained in:
abejgonzalez
2021-03-21 15:34:01 -07:00
parent 55263971bc
commit 5ffad327db
4 changed files with 4 additions and 3 deletions
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1
.circleci/config.yml
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@@ -308,6 +308,7 @@ jobs:
tools-version: "esp-tools" tools-version: "esp-tools"
group-key: "group-accels" group-key: "group-accels"
project-key: "chipyard-hwacha" project-key: "chipyard-hwacha"
timeout: "30m"
chipyard-gemmini-run-tests: chipyard-gemmini-run-tests:
executor: main-env executor: main-env
steps: steps:

2
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -130,7 +130,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
val harnessMultiClockAXIRAM = withClockAndReset(th.harnessClock, th.harnessReset) { val harnessMultiClockAXIRAM = withClockAndReset(th.harnessClock, th.harnessReset) {
SerialAdapter.connectHarnessMultiClockAXIRAM( SerialAdapter.connectHarnessMultiClockAXIRAM(
system.serdesser.get, system.serdesser.get,
port, serial_bits,
axiClockBundle, axiClockBundle,
th.harnessReset) th.harnessReset)
} }

2
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -95,7 +95,7 @@ class WithFireSimDefaultFrequencyTweaks extends Config(
// runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithAsynchrousMemoryBusCrossing ++ new chipyard.config.WithAsynchrousMemoryBusCrossing ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++ new testchipip.WithAsynchronousSerialSlaveCrossing
) )
// Tweaks that are generally applied to all firesim configs // Tweaks that are generally applied to all firesim configs

2
generators/testchipip

Submodule generators/testchipip updated: ef59e54c42...1d2ac9c13b