Merge branch 'dev' into howie-docs

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -8,12 +8,13 @@ Generators
 
 The Chipyard Framework currently consists of the following RTL generators:
 
+
 Processor Cores
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-**Rocket**
+**Rocket Core**
   An in-order RISC-V core.
-  See :ref:`Rocket` for more information.
+  See :ref:`Rocket Core` for more information.
 
 **BOOM (Berkeley Out-of-Order Machine)**
   An out-of-order RISC-V core.

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -1,6 +1,13 @@
 Initial Repository Setup
 ========================================================
 
+Requirements
+-------------------------------------------
+
+Chipyard is developed and tested on Linux-based systems.
+It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
+Working under Windows is not recommended.
+
 Checking out the sources
 ------------------------
 
@@ -28,6 +35,6 @@ But to get a basic installation, just the following steps are necessary.
 
     ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions
 
-Once the script is run, a ``env.sh`` file is emitted at sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables.
+Once the script is run, a ``env.sh`` file is emitted that sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables.
 You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables.
 These variables need to be set for the make system to work properly.

docs/Chipyard-Basics/index.rst

@@ -20,5 +20,3 @@ Hit next to get started!
    Chipyard-Components
    Configs-Parameters-Mixins
    Initial-Repo-Setup
-   Running-A-Simulation
-   Building-A-Chip

docs/Customization/Memory-Hierarchy.rst

@@ -1,3 +1,5 @@
+.. _memory-hierarchy:
+
 Memory Hierarchy
 ===============================
 

docs/Generators/Hwacha.rst

@@ -2,7 +2,14 @@ Hwacha
 ====================================
 
 The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
-Inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures Scale and Maven, we are bringing back elegant, performant, and energy-efficient aspects of vector processing to modern data-parallel architectures.
-We propose a new vector-fetch architectural paradigm, which focuses on the following aspects for higher performance, better energy efficiency, and lower complexity.
+The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven
+The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
 
-For more information, please visit the `Hwacha website <http://hwacha.org/>`__.
+For more information on the Hwacha project, please visit the `Hwacha website <http://hwacha.org/>`__.
+
+To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config mixin to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). 
+
+To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala <https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/configs.scala>`__ to see the possible configuration parameters.
+ 
+Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and asseble its vector instructions.
+To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it.

docs/Generators/Rocket-Chip.rst

@@ -1,15 +1,15 @@
-RocketChip
-==========
+Rocket Chip
+===========
 
-RocketChip is an SoC generator developed at Berkeley and now supported by
-SiFive. Chipyard uses RocketChip as the basis for producing a RISC-V SoC.
+Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
+SiFive. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
 
-RocketChip is distinct from Rocket, the in-order RISC-V CPU generator.
-RocketChip includes many parts of the SoC besides the CPU. Though RocketChip
-uses Rocket CPUs by default, it can also be configured to use the BOOM
+`Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
+Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip
+uses Rocket core CPUs by default, it can also be configured to use the BOOM
 out-of-order core generator or some other custom CPU generator instead.
 
-A detailed diagram of a typical RocketChip system is shown below.
+A detailed diagram of a typical Rocket Chip system is shown below.
 
 .. image:: ../_static/images/rocketchip-diagram.png
 

docs/Generators/Rocket.rst

@@ -1,8 +1,9 @@
-Rocket
+Rocket Core
 ====================================
 
-`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar core generator that is supported by `SiFive <https://www.sifive.com/>`__.
-It supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
+`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive <https://www.sifive.com/>`__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
+
+The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
 It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
 Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS).
 For floating-point,  Rocket  makes  use  of  Berkeley’s  Chisel  implementations  of  floating-point  units.

docs/Generators/SHA3.rst

@@ -0,0 +1,80 @@
+SHA3 RoCC Accelerator
+===================================
+The SHA3 accelerator is a basic RoCC accelerator for the SHA3 hashing algorithm.
+We like using SHA3 in Chipyard tutorial content because it is a self-contained, simple
+example of integrating a custom accelerator into Chipyard.
+
+
+Introduction
+-----------------------------------
+Secure hashing algorithms represent a class of hashing functions that provide four attributes: ease
+of hash computation, inability to generate the message from the hash (one-way property), inability
+to change the message and not the hash (weakly collision free property), and inability to find
+two messages with the same hash (strongly collision free property). The National Institute of
+Standards and Technology (NIST) recently held a competition for a new algorithm to be added to
+its set of Secure Hashing Algorithms (SHA). In 2012 the winner was determined to be the Keccak
+hashing function and a rough specification for SHA3 was established. The algorithm operates on
+variable length messages with a sponge function, and thus alternates between absorbing chunks of
+the message into a set of state bits and permuting the state. The absorbing is a simple bitwise
+XOR while the permutation is a more complex function composed of several operations, χ, θ, ρ,
+π, ι, that all perform various bitwise operations, including rotations, parity calculations, XORs,
+etc. The Keccak hashing function is parameterized for different sizes of state and message chunks
+but for this accelerator we will only support the Keccak-256 variant with 1600 bits of state and
+1088 bit message chunks. A diagram of the SHA3 accelerator is shown below.
+
+.. image:: ../_static/images/sha3.png
+
+Technical Details
+------------------------------------
+The accelerator is designed around three sub-systems, an
+interface with the processor, an interface with memory, and
+the actual hashing computation system. The interface
+with the processor is designed using the ROCC interface for
+coprocessors integrating with the RISC-V Rocket/BOOM
+processor. It includes the ability to transfer two 64 bit
+words to the co-processor, the request for a return value,
+and a small field for the function requested. The accelerator
+receives these requests using a ready/valid interface. The
+ROCC instruction is parsed and the needed information is
+stored into a execution context. The execution context contains
+the memory address of the message being hashed, the memory address
+to store the resulting hash in, the length of the message, and
+several other control fields.
+
+Once the execution context is valid the memory subsystem
+then begins to fetch chunks of the message. The memory
+subsystem is fully decoupled from the other subsystems
+and maintains a single full round memory buffers.
+The accelerators memory interface can provide a
+maximum of one 64 bit word per cycle which corresponds
+to 17 requests needed to fill a buffer (the size is dictated by
+the SHA3 algorithm). Memory requests to fill these buffers
+are sent out as rapidly as the memory interface can handle,
+with a tag field set to allow the different memory buffers
+requests to be distinguished, as they may be returned out of
+order. Once the memory subsystem has filled a buffer the
+control unit absorbs the buffer into the execution
+context, at which point the execution context is free to
+begin permutation, and the memory buffer is free to send
+more memory requests.
+
+After the buffer is absorbed, the hashing computation
+subsystem begins the permutation operations. Once
+the message is fully hashed, the hash is written to memory
+with a simple state machine.
+
+
+Using a SHA3 Accelerator
+------------------------
+Since the SHA3 accelerator is designed as a RoCC accelerator,
+it can be mixed into a Rocket or BOOM core by overriding the
+BuildRoCC key. The configuration mixin is defined in the SHA3
+generator. An example configuration highlighting the use of
+this mixin is shown here:
+
+.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
+   :language: scala
+   :start-after: DOC include start: Sha3Rocket
+   :end-before: DOC include end: Sha3Rocket
+
+

docs/Generators/SiFive-Generators.rst

@@ -0,0 +1,45 @@
+SiFive Generators
+==================
+
+Chipyard includes several open-source generators developed and maintained by `SiFive <https://www.sifive.com/>`__. 
+These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
+
+Last-Level Cache Generator
+-----------------------------
+
+``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` mixin to your SoC configuration.
+To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
+
+
+Peripheral Devices
+-------------------
+``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
+
+These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
+To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. 
+
+.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala
+    :language: scala
+    :start-after: DOC include start: WithGPIO
+    :end-before: DOC include end: WithGPIO
+
+Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC.
+When adding a top-level IO, you should also be aware of whether it interacts with the test-harness.
+For example, a GPIO device would require a GPIO pin, and therefore we would write a mixin to augment the top level as follows:
+
+.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala
+    :language: scala
+    :start-after: DOC include start: WithGPIOTop
+    :end-before: DOC include end: WithGPIOTop
+
+This example instantiates a top-level module with include GPIO ports (``TopWithGPIO``), and then ties-off the GPIO port inputs to 0 (``false.B``).
+
+
+Finally, you add the relevant config mixin to the SoC config. For example:
+
+.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
+    :language: scala
+    :start-after: DOC include start: GPIORocketConfig
+    :end-before: DOC include end: GPIORocketConfig
+
+Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined mixins within the Chipyard example project. You may be able to use these config mixins directly, but you should be aware of their addresses within the SoC address map. 

docs/Generators/index.rst

@@ -1,19 +1,28 @@
+.. _generator-index:
+
 Generators
 ============================
 
-Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL.
+A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL.
 This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`).
 A standard RTL design is essentially just a single instance of a design coming from a generator.
 However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways.
 The following pages introduce the generators integrated with the Chipyard framework.
 
+Chipyard bundles the source code for the generators, under the ``generators`` directory.
+It builds them from source each time (although the build system will cache results if they have not changed),
+so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows.
+
+
 .. toctree::
    :maxdepth: 2
    :caption: Generators:
 
+   Rocket-Chip
    Rocket
    BOOM
    Hwacha
-   RocketChip
    IceNet
    TestChipIP
+   SiFive-Generators   
+   SHA3

docs/Quick-Start.rst

@@ -1,6 +1,13 @@
 Quick Start
 ===============================
 
+Requirements
+-------------------------------------------
+
+Chipyard is developed and tested on Linux-based systems.
+It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
+Working under Windows is not recommended.
+
 Setting up the Chipyard Repo
 -------------------------------------------
 
@@ -39,16 +46,18 @@ What's Next?
 
 This depends on what you are planning to do with Chipyard.
 
-* To learn about the structure of Chipyard, see :ref:`chipyard-components`.
+* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions.
 
-* To build one of the vanilla Chipyard examples, see :ref:`build-a-chip`.
+* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`sw-sim-custom` and follow the instructions.
 
-* To add a new accelerator, see :ref:`adding-an-accelerator`.
+* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions.
 
-* To run a simulation of one of the Chipyard examples, see :ref:`sw-rtl-sim-intro`.
+* If you intend to add a new accelerator, go to :ref:`adding-an-accelerator` and follow the instructions.
 
-* To run a simulation of a custom Chipyard SoC Configuration, see <>.
+* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`.
 
-* To run a FPGA-accelerated simulation using FireSim, see :ref:`firesim-sim-intro`.
+* If you intend to build one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions.
 
-* To run a VLSI flow using one of the vanilla Chipyard examples, see <>.
+* If you intend to run a VLSI flow using one of the vanilla Chipyard examples, go to <> and follow the instructions.
+
+* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`.

docs/Simulation/Running-A-Simulation.rst

@@ -39,13 +39,21 @@ In order to construct the simulator with our custom design, we run the following
     make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=...
 
 Each of these make variables correspond to a particular part of the design/codebase and are needed so that the make system can correctly build and make a RTL simulation.
+
 The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build.
+
 The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design.
+
 Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
+
 The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class.
+
 The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in.
+
 The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design.
+
 The ``TB`` is the name of the Verilog wrapper that connects the ``TestHarness`` to VCS/Verilator for simulation.
+
 Finally, the ``TOP`` variable is used to distinguish between the top-level of the design and the ``TestHarness`` in our system.
 For example, in the normal case, the ``MODEL`` variable specifies the ``TestHarness`` as the top-level of the design.
 However, the true top-level design, the SoC being simulated, is pointed to by the ``TOP`` variable.

docs/Simulation/Software-RTL-Simulation.rst

@@ -0,0 +1,139 @@
+.. _sw-rtl-sim-intro:
+
+Software RTL Simulation
+===================================
+
+Verilator (Open-Source)
+-----------------------
+
+`Verilator <https://www.veripool.org/wiki/verilator>`__ is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__.
+The Chipyard framework can download, build, and execute simulations using Verilator.
+
+
+Synopsys VCS (License Required)
+--------------------------------
+
+`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`__ is a commercial RTL simulator developed by Synopsys.
+It requires commercial licenses.
+The Chipyard framework can compile and execute simulations using VCS.
+VCS simulation will generally compile faster than Verilator simulations.
+
+To run a VCS simulation, make sure that the VCS simulator is on your ``PATH``.
+
+
+Choice of Simulator
+-------------------------------
+
+First, we will start by entering the Verilator or VCS directory:
+
+For an open-source Verilator simulation, enter the ``sims/verilator`` directory
+.. code-block:: shell
+
+    # Enter Verilator directory
+    cd sims/verilator
+
+For a proprietry VCS simulation, enter the ``sims/vcs`` directory
+
+.. code-block:: shell
+
+    # Enter VCS directory
+    cd sims/vcs
+
+
+.. _sim-default:
+Simulating The Default Example
+-------------------------------
+
+To compile the example design, run ``make`` in the selected verilator or VCS directory.
+This will elaborate the ``RocketConfig`` in the example project.
+
+An executable called ``simulator-example-RocketConfig`` will be produced.
+This executable is a simulator that has been compiled based on the design that was built.
+You can then use this executable to run any compatible RV64 code.
+For instance, to run one of the riscv-tools assembly tests.
+
+.. code-block:: shell
+
+    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+
+.. Note:: in a VCS simulator, the simulator name will be ``simv-example-RocketConfig`` ``instead of simulator-example-RocketConfig``.
+
+Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``.
+For example:
+
+.. code-block:: shell
+
+    make run-asm-tests
+    make run-bmark-tests
+
+
+.. Note:: Before running the pre-packaged suites, you must run the plain ``make`` command, since the elaboration command generates a Makefile fragment that contains the target for the pre-packaged test suites. Otherwise, you will likely encounter a Makefile target error.
+
+
+.. _sw-sim-custom:
+Simulating A Custom Project
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+If you later create your own project, you can use environment variables to build an alternate configuration.
+
+In order to construct the simulator with our custom design, we run the following command within the simulator directory:
+
+.. code-block:: shell
+
+    make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=...
+
+Each of these make variables correspond to a particular part of the design/codebase and are needed so that the make system can correctly build and make a RTL simulation.
+
+The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build.
+
+The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design.
+
+Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
+
+The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class.
+
+The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in.
+
+The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design.
+
+The ``TB`` is the name of the Verilog wrapper that connects the ``TestHarness`` to VCS/Verilator for simulation.
+
+Finally, the ``TOP`` variable is used to distinguish between the top-level of the design and the ``TestHarness`` in our system.
+For example, in the normal case, the ``MODEL`` variable specifies the ``TestHarness`` as the top-level of the design.
+However, the true top-level design, the SoC being simulated, is pointed to by the ``TOP`` variable.
+This separation allows the infrastructure to separate files based on the harness or the SoC top level.
+
+Common configurations of all these variables are packaged using a ``SUB_PROJECT`` make variable.
+Therefore, in order to simulate a simple Rocket-based example system we can use:
+
+
+.. code-block:: shell
+
+    make SUB_PROJECT=yourproject
+    ./simulator-<yourproject>-<yourconfig> ...
+
+
+All `Make` targets that can be applied to the default example, can also be applied to custom project using the custom environment variables. For example, the following code example will run the RISC-V assembly benchmark suite on the Hwacha subproject:
+
+.. code-block:: shell
+
+    make SUB_PROJECT=hwacha run-asm-tests
+
+
+Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral and Verilog source files for the build/simulation.
+Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``.
+
+
+Generating Waveforms
+-----------------------
+
+If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
+
+
+For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
+An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
+
+
+For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
+If you have Synopsys licenses, we recommend using the DVE waveform viewer.
+

docs/Simulation/Software-RTL-Simulators.rst

@@ -1,75 +0,0 @@
-.. _sw-rtl-sim-intro:
-
-Software RTL Simulators
-===================================
-
-Verilator (Open-Source)
------------------------
-
-`Verilator <https://www.veripool.org/wiki/verilator>`__ is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__.
-The Chipyard framework can download, build, and execute simulations using Verilator.
-
-To run a simulation using Verilator, perform the following steps:
-
-To compile the example design, run ``make`` in the ``sims/verilator`` directory.
-This will elaborate the ``RocketConfig`` in the example project.
-
-An executable called ``simulator-example-RocketConfig`` will be produced.
-This executable is a simulator that has been compiled based on the design that was built.
-You can then use this executable to run any compatible RV64 code.
-For instance, to run one of the riscv-tools assembly tests.
-
-.. code-block:: shell
-
-    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
-
-If you later create your own project, you can use environment variables to build an alternate configuration.
-
-.. code-block:: shell
-
-    make SUB_PROJECT=yourproject
-    ./simulator-<yourproject>-<yourconfig> ...
-
-If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
-This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
-An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
-
-Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.
-Commercial Software RTL Simulators
-
-Synopsys VCS (License Required)
---------------------------------
-
-`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`__ is a commercial RTL simulator developed by Synopsys.
-It requires commercial licenses.
-The Chipyard framework can compile and execute simulations using VCS.
-VCS simulation will generally compile faster than Verilator simulations.
-
-To run a simulation using VCS, perform the following steps:
-
-Make sure that the VCS simulator is on your ``PATH``.
-
-To compile the example design, run make in the ``sims/vcs`` directory.
-This will elaborate the ``RocketConfig`` in the example project.
-
-An executable called ``simulator-example-RocketConfig`` will be produced.
-This executable is a simulator that has been compiled based on the design that was built.
-You can then use this executable to run any compatible RV64 code.
-For instance, to run one of the riscv-tools assembly tests.
-
-.. code-block:: shell
-
-    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
-
-If you later create your own project, you can use environment variables to build an alternate configuration.
-
-.. code-block:: shell
-
-    make SUB_PROJECT=yourproject
-    ./simulator-<yourproject>-<yourconfig> ...
-
-If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
-This will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
-If you have Synopsys licenses, we recommend using the DVE waveform viewer.
-
-Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.

docs/Simulation/index.rst

@@ -1,4 +1,4 @@
-Simulators
+Simulation
 =======================
 
 Chipyard supports two classes of simulation:
@@ -12,9 +12,11 @@ at O(100 MHz), making them appropriate for booting an operating system and
 running a complete workload, but have multi-hour compile times and poorer debug
 visability.
 
+Click next to see how to run a simulation.
+
 .. toctree::
    :maxdepth: 2
-   :caption: Simulators:
+   :caption: Simulation:
 
-   Software-RTL-Simulators
+   Software-RTL-Simulation
    FPGA-Accelerated-Simulators

docs/Software/FireMarshal.rst

@@ -0,0 +1,23 @@
+FireMarshal
+=================
+
+FireMarshal is a workload generation tool for RISC-V based systems. It
+currently only supports the FireSim FPGA-accelerated simulation platform.
+
+**Workloads** in FireMarshal consist of a series of **Jobs** that are assigned
+to logical nodes in the target system. If no jobs are specified, then the
+workload is considered ``uniform`` and only a single image will be produced for
+all nodes in the system. Workloads are described by a ``json`` file and a
+corresponding workload directory and can inherit their definitions from
+existing workloads. Typically, workload configurations are kept in
+``workloads/`` although you can use any directory you like. We provide a few
+basic workloads to start with including buildroot or Fedora-based linux
+distributions and bare-metal.
+
+Once you define a workload, the ``marshal`` command will produce a
+corresponding boot-binary and rootfs for each job in the workload. This binary
+and rootfs can then be launched on qemu or spike (for functional simulation), or
+installed to a platform for running on real RTL (currently only FireSim is
+automated).
+
+To get started, checkout the full `FireMarshal documentation <https://firemarshal.readthedocs.io/en/latest/index.html>`_.

docs/Software/Spike.rst

@@ -0,0 +1,4 @@
+The RISC-V ISA Simulator (Spike)
+=================================
+
+.. attention:: This article is a stub. Fill it out!

docs/Software/index.rst

@@ -0,0 +1,21 @@
+Target Software
+==================================
+
+Chipyard includes tools for developing target software workloads. The primary
+tool is FireMarshal, which manages workload descriptions and generates binaries
+and disk images to run on your target designs. Workloads can be bare-metal, or
+be based on standard Linux distributions. Users can customize every part of the
+build process, including providing custom kernels (if needed by the hardware).
+
+FireMarshal can also run your workloads on high-performance functional
+simulators like Spike and Qemu. Spike is easily customized and serves as the
+official RISC-V ISA reference implementation. Qemu is a high-performance
+functional simulator that can run nearly as fast as native code, but can be
+challenging to modify.
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   FireMarshal
+   Spike

docs/Tools/Treadle.rst

@@ -1,5 +1,9 @@
-Treadle
+Treadle and FIRRTL Interpreter
 ==============================
 
-`Treadle <https://github.com/freechipsproject/treadle>`__ is a circuit simulator that directly executes FIRRTL.
-It is especially useful for interactive debugging and small unit tests that benefit from a low-overhead simulator.
+`Treadle <https://github.com/freechipsproject/treadle>`__ and
+`FIRRTL Interpreter <https://github.com/freechipsproject/firrtl-interpreter>`__
+are circuit simulators that directly execute FIRRTL (specifically low-firrtl IR).
+Treadle is the replacement for FIRRTL Interpreter but FIRRTL Interpreter is still used within some
+projects. Treadle is useful for simulating modules in a larger SoC design. Many projects
+use Treadle for interactive debugging and a low-overhead simulator.

docs/VLSI/index.rst

@@ -8,4 +8,5 @@ In particular, we aim to support the HAMMER physical design generator flow.
    :maxdepth: 2
    :caption: VLSI Flow:
 
+   Building-A-Chip
    HAMMER

docs/index.rst

@@ -38,6 +38,8 @@ Table of Contents
 
    Customization/index
 
+   Software/index
+
    Advanced-Usage/index
 
    TileLink-Diplomacy-Reference/index

generators/example/src/main/scala/ConfigMixins.scala

@@ -37,6 +37,7 @@ class WithBootROM extends Config((site, here, up) => {
     contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
 })
 
+// DOC include start: WithGPIO
 /**
  * Class to add in GPIO
  */
@@ -44,6 +45,7 @@ class WithGPIO extends Config((site, here, up) => {
   case PeripheryGPIOKey => List(
     GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
 })
+// DOC include end: WithGPIO
 
 // -----------------------------------------------
 // BOOM and/or Rocket Top Level System Parameter Mixins
@@ -107,6 +109,7 @@ class WithSimBlockDeviceTop extends Config((site, here, up) => {
   }
 })
 
+// DOC include start: WithGPIOTop
 /**
  * Class to specify a top level BOOM and/or Rocket system with GPIO
  */
@@ -121,6 +124,7 @@ class WithGPIOTop extends Config((site, here, up) => {
     top
   }
 })
+// DOC include end: WithGPIOTop
 
 // ------------------
 // Multi-RoCC Support

generators/example/src/main/scala/RocketConfigs.scala

@@ -50,7 +50,7 @@ class PWMRocketConfig extends Config(
   new freechips.rocketchip.system.BaseConfig)
 // DOC include end: PWMRocketConfig
 
-class PWMRAXI4ocketConfig extends Config(
+class PWMAXI4RocketConfig extends Config(
   new WithPWMAXI4Top ++                                    // use top with axi4-controlled PWM
   new WithBootROM ++
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
@@ -73,6 +73,7 @@ class BlockDeviceModelRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
+// DOC include start: GPIORocketConfig
 class GPIORocketConfig extends Config(
   new WithGPIO ++                                          // add GPIOs to the peripherybus
   new WithGPIOTop ++                                       // use top with GPIOs
@@ -80,6 +81,7 @@ class GPIORocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
+// DOC include end: GPIORocketConfig
 
 class DualCoreRocketConfig extends Config(
   new WithTop ++
@@ -104,6 +106,7 @@ class GB1MemoryRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
+// DOC include start: Sha3Rocket
 class Sha3RocketConfig extends Config(
   new WithTop ++
   new WithBootROM ++
@@ -111,6 +114,7 @@ class Sha3RocketConfig extends Config(
   new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
+// DOC include end: Sha3Rocket
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(