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Merge pull request #1324 from ucb-bar/new-hammer

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New Hammer
This commit is contained in:
Harrison Liew
2023-02-15 13:14:01 -08:00
committed by GitHub
parent a1a1a49429 a998754020
commit 660c63fb34
37 changed files with 5104 additions and 4533 deletions
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5
.github/scripts/check-commit.sh vendored
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@@ -98,11 +98,6 @@ dir="sims"
branches=("master" "main" "dev" "1.13.x")
search
submodules=("hammer")
dir="vlsi"
branches=("master")
search
submodules=("fpga-shells")
dir="fpga"
branches=("main")

3
.gitmodules vendored
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@@ -28,9 +28,6 @@
[submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "vlsi/hammer"]
path = vlsi/hammer
url = https://github.com/ucb-bar/hammer.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git

2
.pre-commit-config.yaml
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@@ -2,7 +2,7 @@
# See https://pre-commit.com/hooks.html for more hooks
repos:
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v3.2.0
rev: v4.4.0
hooks:
- id: trailing-whitespace
- id: end-of-file-fixer

20
common.mk
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@@ -177,11 +177,13 @@ endif
--annotation-file $(FINAL_ANNO_FILE) \
--log-level $(FIRRTL_LOGLEVEL) \
--allow-unrecognized-annotations \
-DX $(SFC_LEVEL) \
-X $(SFC_LEVEL) \
$(EXTRA_FIRRTL_OPTIONS))
$(EXTRA_FIRRTL_OPTIONS)) # -X and -DX are duplicates to allow for extra FIRRTL passes to be run
-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
@if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi
firtool \
--format=fir \
--dedup \
@@ -192,7 +194,7 @@ endif
--disable-annotation-classless \
--disable-annotation-unknown \
--mlir-timing \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
--repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--repl-seq-mem-circuit=$(MODEL) \
@@ -218,6 +220,14 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
$(SED) -i 's/\.\///' $(BB_MODS_FILELIST)
sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST)
$(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE)
$(base_dir)/scripts/split-bb-files.py \
--in-bb-f $(BB_MODS_FILELIST) \
--in-top-hrchy-json $(MFC_TOP_HRCHY_JSON) \
--in-anno-json $(FINAL_ANNO_FILE) \
--out-top-bb-f $(TOP_BB_MODS_FILELIST) \
--out-model-bb-f $(MODEL_BB_MODS_FILELIST)
$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON)
$(base_dir)/scripts/split-mems-conf.py \
--in-smems-conf $(MFC_SMEMS_CONF) \
@@ -238,8 +248,10 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE
########################################################################################
# remove duplicate files and headers in list of simulation file inputs
# note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated,
# however it is really unneeded since ALL_MODS_FILELIST includes all BB files
########################################################################################
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE)
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST)
sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
echo "$(TOP_SMEMS_FILE)" >> $@
echo "$(MODEL_SMEMS_FILE)" >> $@

7
conda-reqs/chipyard.yaml
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@@ -29,10 +29,10 @@ dependencies:
- binutils
- dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo
- firtool>=1.25 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
- firtool==1.30.0 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
# firemarshal deps
- python>=3.8
- python>=3.9
- bc
- patch
- which
@@ -91,6 +91,7 @@ dependencies:
- wget
- sed
- autoconf
- pre-commit
# clang-format for driver coding style enforcement.
- clang-format
@@ -121,12 +122,14 @@ dependencies:
- boto3-stubs==1.21.6
- botocore-stubs==1.24.7
- mypy-boto3-s3==1.21.0
- sty==1.0.0
- pip
- pip:
- fab-classic==1.19.1
- mypy-boto3-ec2==1.21.9
- sure==2.0.0
- pylddwrap==1.2.1
- hammer-vlsi[asap7]==1.0.1
# doc requirements
- sphinx

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conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml generated
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conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml generated
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134
conda-requirements-riscv-tools.yaml
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@@ -1,134 +0,0 @@
channels:
- ucb-bar
- conda-forge
- nodefaults
dependencies:
# https://conda-forge.org/feedstock-outputs/
# filterable list of all conda-forge packages
# https://conda-forge.org/#contribute
# instructions on adding a recipe
# https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
# documentation on package_spec syntax for constraining versions
# handy tool for introspecting package relationships and file ownership
# see https://github.com/rvalieris/conda-tree
- conda-tree
# bundle FireSim driver with deps into installer shell-script
- constructor
- gcc
- gxx
- sysroot_linux-64>=2.17 # needed to match pre-built CI XRT glibc version
- conda-gcc-specs
- binutils
- dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo
- riscv-tools=1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
- firtool # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
# firemarshal deps
- python>=3.8
- bc
- patch
- which
- diffutils
- bash
- gzip
- bzip2
- perl
- tar
- file
- findutils
- rsync
- psutil
- doit=0.35.0
- gitpython
- humanfriendly
- e2fsprogs
- ctags
- bison
- flex
- expat
- make
- pyyaml
- unzip
- readline
- coreutils
- lzop
- qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock
- jq
- bash-completion
- sbt
- ca-certificates
- mosh
- gmp
- mpfr
- mpc
- zlib
- vim
- git
- openjdk
- gengetopt
- libffi
- expat
- libusb1
- ncurses
- cmake
- graphviz
- expect
- dtc
- verilator==4.226
- screen
- elfutils
- libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
- conda-lock>=1
- wget
- sed
- autoconf
# clang-format for driver coding style enforcement.
- clang-format
- clang-tools
# python packages
# While it is possible to install using pip after creating the
# conda environment, pip's dependency resolution can conflict with
# conda and create broken environments. It's best to use the conda
# packages so that the environment is consistent
- boto3==1.20.21
- colorama==0.4.3
- argcomplete==1.12.3
- python-graphviz==0.19
- pyparsing==3.0.6
- numpy==1.19.5
- kiwisolver==1.3.1
- matplotlib-base==3.3.4
- pandas==1.1.5
- awscli==1.22.21
- pytest==6.2.5
- pytest-dependency==0.5.1
- pytest-mock==3.7.0
- moto==3.1.0
- pyyaml==5.4.1
- mypy==0.931
- types-pyyaml==6.0.4
- boto3-stubs==1.21.6
- botocore-stubs==1.24.7
- mypy-boto3-s3==1.21.0
- pip
- pip:
- fab-classic==1.19.1
- mypy-boto3-ec2==1.21.9
- sure==2.0.0
- pylddwrap==1.2.1
# doc requirements
- sphinx
- pygments
- sphinx-autobuild
- sphinx_rtd_theme
- docutils

4
docs/Chipyard-Basics/Initial-Repo-Setup.rst
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@@ -49,6 +49,8 @@ This is done by the following:
conda install -n base conda-lock
conda activate base
.. Note:: We also recommended switching to `libmamba <https://www.anaconda.com/blog/a-faster-conda-for-a-growing-community>`__ for much faster dependency solving.
Setting up the Chipyard Repo
-------------------------------------------
@@ -103,6 +105,8 @@ This file activates the conda environment created in ``build-setup.sh`` and sets
Once the script is run, the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables will be set properly for the toolchain requested.
You can source this file in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment:
.. Note:: If you are on a Mac or a RHEL/CentOS-based Linux distribution, you must deactivate the base conda environment with ``conda deactivate`` first before proceeding. You may also choose to keep it deactivated by default with ``conda config --set auto_activate_base false``. See this `issue <https://github.com/conda/conda/issues/9392>`__ for more details.
.. code-block:: shell
source ./env.sh

27
docs/VLSI/ASAP7-Tutorial.rst
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@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``env.yml``
* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
* ``example-vlsi``
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``example-asap7.yml``, ``example-tools.yml``
* Hammer IR for this tutorial.
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
* ``example-design.yml``, ``example-sky130.yml``, ``example-tech.yml``
@@ -38,9 +38,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
* ``hammer-<vendor>-plugins``
* Core, tool, tech repositories.
* Tool plugin repositories.
* ``view_gds.py``
@@ -49,31 +49,22 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
Prerequisites
-------------
* Python 3.4+
* numpy and `gdstk <https://github.com/heitzmann/gdstk>`__ or `gdspy <https://github.com/heitzmann/gdspy>`__ packages. Note: gdspy must be version 1.4.
* Python 3.9+
* Genus, Innovus, Voltus, VCS, and Calibre licenses
* For ASAP7 specifically (`README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ for more details):
* For ASAP7 specifically (`README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__ for more details):
* First, download the `ASAP7 v1p7 PDK <https://github.com/The-OpenROAD-Project/asap7>`__ (we recommend shallow-cloning or downloading an archive of the repository). Then, download the `encrypted Calibre decks tarball <http://asap.asu.edu/asap/>`__ tarball to a directory of choice (e.g. the root directory of the PDK) but do not extract it like the instructions say. The tech plugin is configured to extract the tarball into a cache directory for you.
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision.
Initial Setup
-------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
.. code-block:: shell
./scripts/init-vlsi.sh asap7
to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Building the Design
--------------------
@@ -139,7 +130,7 @@ To run DRC & LVS, and view the results in Calibre:
make lvs CONFIG=TinyRocketConfig
./build/lvs-rundir/generated-scripts/view-lvs
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__.
Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors.
Simulation

42
docs/VLSI/Advanced-Usage.rst
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@@ -3,6 +3,14 @@
Advanced Usage
==============
Hammer Development
------------------
If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
.. code-block:: shell
pip install -e <path/to/hammer>
Alternative RTL Flows
---------------------
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
@@ -39,37 +47,51 @@ For more information about all the options that can be passed to the Hammer comm
Manual Step Execution & Dependency Tracking
-------------------------------------------
It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--stop_after_step``, ``--start_before_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command.
Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
Say you need to update some power straps settings in ``new_power_straps.yml`` and want to try out the new settings:
.. code-block:: shell
make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
make redo-par HAMMER_REDO_ARGS='-p new_power_straps.yml --only_step power_straps'
The command that is executed will be:
.. code-block:: shell
./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json -p new_power_straps.yml --only_step power_straps --obj_dir /path/to/build par
Hierarchical RTL/Gate-level Simulation, Power Estimation
--------------------------------------------------------
With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, rtl-level/post-syn power estimation with Joules and post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
* ``sim-rtl``: RTL-level simulation
* ``sim-rtl-debug``: Also write a VPD waveform
* ``sim-rtl-debug``: Also write a FSDB waveform
* ``sim-syn``: Post-synthesis gate-level simulation
* ``sim-syn-debug``: Also write a VPD waveform
* ``sim-syn-timing-debug``: Timing-annotated with VPD waveform
* ``sim-syn-debug``: Also write a FSDB waveform
* ``sim-syn-timing-debug``: Timing-annotated with FSDB waveform
* ``sim-par``: Post-par gate-level simulation
* ``sim-par-debug``: Also write a VPD waveform
* ``sim-par-timing-debug``: Timing-annotated with VPD waveform
* ``sim-par-debug``: Also write a FSDB waveform
* ``sim-par-timing-debug``: Timing-annotated with FSDB waveform
* ``power-rtl``: RTL-level power estimation
* Note: this will run ``sim-rtl-debug`` first
* ``power-syn``: Post-synthesis power estimation
* Note: this will run ``sim-syn-debug`` first
* ``power-par``: Post-par power estimation
* Note: this will run ``sim-par`` first
* Note: this will run ``sim-par-debug`` first
* ``redo-`` can be appended to all above targets to break dependency tracking, like described above.

29
docs/VLSI/Basic-Flow.rst
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@@ -7,32 +7,26 @@ Using Hammer To Place and Route a Custom Block
Initialize the Hammer Plug-ins
----------------------------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, depending on if you are using a technology plugin included with Hammer (ASAP7, Sky130) or as a separate plugin, you will run either of the commands below.
For Hammer-provided plugins (``<tech-plugin-name>`` is ``asap7`` or ``sky130``):
.. code-block:: shell
./scripts/init-vlsi.sh <tech-plugin-name>
This will pull the Hammer & CAD tool plugin submodules, assuming the technology plugins are available on github.
Currently only the asap7 technology plugin is available on github.
If you have additional private technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), you can clone them directly
into VLSI directory with the name ``hammer-<tech-plugin-name>-plugin``.
For separate technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), submodule them directly
into VLSI directory with the name ``hammer-<tech-plugin-name>-plugin`` before calling the ``init-vlsi.sh`` script.
For example, for an imaginary process technology called tsmintel3:
.. code-block:: shell
cd vlsi
git clone git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git
Next, we define the Hammer environment into the shell:
.. code-block:: shell
cd vlsi # (if you haven't done so yet)
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
git submodule add git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git
cd -
./scripts/init-vlsi.sh tsmintel3
If submoduled plugins need to be updated, call the ``upgrade-vlsi.sh`` script. This will checkout and pull the latest master branch.
.. Note:: Some VLSI EDA tools are supported only on RHEL-based operating systems. We recommend using Chipyard on RHEL7 and above. However, many VLSI server still have old operating systems such as RHEL6, which have software packages older than the basic chipyard requirements. In order to build Chipyard on RHEL6, you will likely need to use tool packages such as devtoolset (for example, devtoolset-8) and/or build from source gcc, git, gmake, make, dtc, cc, bison, libexpat and liby.
@@ -42,8 +36,7 @@ Setting up the Hammer Configuration Files
The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you only need to fill in the paths for the tools that you will be using.
If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`VLSI/Basic-Flow:Advanced Environment Setup` segment of this documentation page.
Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``sky130``
OpenRoad example), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design.
Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the :ref:`tutorial` and the :ref:`sky130-openroad-tutorial`), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design.
The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``.
The ``example-tools.yml`` file configures which EDA tools hammer will use. This example file uses Cadence Innovus, Genus and Voltus, Synopsys VCS, and Mentor Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another.
@@ -52,7 +45,7 @@ The ``example-design.yml`` file contains basic build system information (how man
Finally, the ``example-tech.yml`` file is a template file for a process technology plugin configuration. We will copy this file, and replace its fields with the appropriate process technology details for the tech plugin that we have access to. For example, for the ``asap7`` tech plugin, we will replace the <tech_name> field with "asap7" and the path to the process technology files installation directory. The technology plugin (which for ASAP7 is within Hammer) will define the technology node and other parameters.
We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs (e.g. create tech-tsmintel3.yml from example-tech.yml)
We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs (e.g. create ``tech-tsmintel3.yml`` from ``example-tech.yml``)
Building the Design

3
docs/VLSI/Building-A-Chip.rst
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@@ -49,4 +49,5 @@ Running the VLSI tool flow
--------------------------
For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`.
For setup and instructions for a VLSI tool flow in the context of Chipyard, see :ref:`hammer_basic_flow`.
For specific examples, see :ref:`tutorial`, :ref:`sky130-commercial-tutorial`, and :ref:`sky130-openroad-tutorial`.

15
docs/VLSI/Hammer.rst
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@@ -6,7 +6,7 @@ Core Hammer
`Hammer <https://github.com/ucb-bar/hammer>`__ is a physical design flow which encourages reusability by partitioning physical design specifications into three distinct concerns: design, CAD tool, and process technology. Hammer wraps around vendor specific technologies and tools to provide a single API to address ASIC design concerns.
Hammer allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
For more information, read the `Hammer paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__ and associated documentation.
For more information, read the `Hammer paper <https://dl.acm.org/doi/abs/10.1145/3489517.3530672>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__ and associated documentation.
Hammer implements a VLSI flow using the following high-level constructs:
@@ -30,7 +30,7 @@ VLSI Flow Control
-----------------
Sometimes we want more fine-grained control of the VLSI flow than at the action level.
The Hammer flow supports being able to start/stop before/after any of the steps in a particular action.
See the `Hammer documentation on Flow Control <https://docs.hammer-eda.org/en/latest/Hammer-Use/Flow-Control.html>`__ for a full list and description of the options.
See the `Hammer documentation on Flow Control <https://hammer-vlsi.readthedocs.io/en/latest/Hammer-Use/Flow-Control.html>`__ for a full list and description of the options.
The ``Makefile`` in the ``vlsi`` directory passes this extra information via the ``HAMMER_EXTRA_ARGS`` variable.
This variable can also be used to specify additional YAML configurations that may have
changed or been omitted from the inital build.
@@ -41,7 +41,7 @@ Configuration (Hammer IR)
To configure a Hammer flow, supply a set ``yaml`` or ``json`` configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions.
The current set of all available Hammer APIs is codified `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.
The current set of all available Hammer APIs is codified `here <https://github.com/ucb-bar/hammer/blob/master/hammer/config/defaults.yml>`__.
Tool Plugins
============
@@ -60,10 +60,9 @@ The types of tools (by Hammer names) supported currently include:
Several configuration variables are needed to configure your tool plugin of choice.
First, select which tool to use for each action by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool, e.g. ``vlsi.core.par_tool: "innovus"``.
First, select which tool to use for each action by setting ``vlsi.core.<tool_type>_tool`` to the package name of your tool, e.g. ``vlsi.core.par_tool: "hammer.par.innovus"``.
Then, point Hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
This directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
This package directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tool.
This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``. The class should implement methods for all the tool's steps.
@@ -75,10 +74,10 @@ Technology Plugins
Hammer supports separately managed technology plugins to satisfy NDAs. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``<tech_name>.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run.
The `ASAP7 plugin <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ is a good starting point for setting up a technology plugin because it is an open-source example that is not suitable for taping out a chip. Refer to Hammer's documentation for the schema and detailed setup instructions.
The `ASAP7 plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__ is a good starting point for setting up a technology plugin because it is an open-source example that is not suitable for taping out a chip. Refer to Hammer's documentation for the schema and detailed setup instructions.
Several configuration variables are needed to configure your technology of choice.
First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``.
First, choose the technology package, e.g. ``vlsi.core.technology: hammer.technology.asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir``.
Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user.

29
docs/VLSI/Sky130-Commercial-Tutorial.rst
View File

@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``env.yml``
* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
* ``example-vlsi-sky130``
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``example-sky130.yml``, ``example-tools.yml``, ``example-designs/sky130-commercial.yml``
* Hammer IR for this tutorial.
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
@@ -38,35 +38,26 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
* ``hammer-<vendor>-plugins``
* Core, tool, tech repositories.
* Tool plugin repositories.
Prerequisites
-------------
* Python 3.6+
* numpy package
* Python 3.9+
* Genus, Innovus, Voltus, VCS, and Calibre licenses
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
Initial Setup
-------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
.. code-block:: shell
./scripts/init-vlsi.sh sky130
to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Building the Design
--------------------
@@ -103,7 +94,7 @@ example-sky130.yml
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
for details about the PDK setup.
example-tools.yml
@@ -143,7 +134,7 @@ To run DRC & LVS, and view the results in Calibre:
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.
For this reason, the ``example-vlsi-sky130`` script black-boxes the SRAMs for DRC/LVS analysis.
Simulation

40
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
View File

@@ -18,13 +18,17 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
* ``env.yml``
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
* ``example-vlsi-sky130``
* Entry point to Hammer. Contains example placeholders for hooks.
* ``example-sky130.yml``, ``example-openroad.yml``, ``example-designs/sky130-openroad.yml``
* Hammer IR for this tutorial.
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
@@ -34,15 +38,14 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>``, ``hammer/src/hammer-vlsi/technology/<tech>``
* ``hammer-<vendor>-plugins``
* Core repository, and open-source tool and technology plugins.
* Tool plugin repositories not used for this tutorial (they are provided in the hammer-vlsi package).
Prerequisites
-------------
* Python 3.6+
* numpy package
* Python 3.9+
* OpenROAD flow tools:
* Yosys (synthesis), install `from source <https://yosyshq.net/yosys/download.html>`__ or `using conda <https://anaconda.org/TimVideos/yosys>`__
@@ -50,27 +53,19 @@ Prerequisites
* Magic (DRC), install `from source <http://www.opencircuitdesign.com/magic/install.html>`__
* NetGen (LVS), install `from source <http://www.opencircuitdesign.com/netgen/install.html>`__ or `using conda <https://anaconda.org/conda-forge/netgen>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
Initial Setup
-------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
.. code-block:: shell
./scripts/init-vlsi.sh sky130 openroad
to pull the Hammer submodule. Note that for technologies other than ``sky130`` or ``asap7``, the tech plugin submodule is cloned into the ``vlsi`` folder,
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder,
and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
Building the Design
--------------------
To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
@@ -92,6 +87,7 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
* ``ENABLE_CUSTOM_FIRRTL_PASS = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
Running the VLSI Flow
---------------------
@@ -106,7 +102,7 @@ example-sky130.yml
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.sky130.<sky130A, openram_lib>`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
for details about the PDK setup.
@@ -163,7 +159,7 @@ To run DRC & LVS:
make lvs tutorial=sky130-openroad
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.
VLSI Flow Control
@@ -180,11 +176,11 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
# example of re-running only floorplanning to test out a new floorplan configuration
make redo-par HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-sky130.yml"
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
Documentation
-------------
For more information about Hammer's underlying implementation, visit the `Hammer documentation website <https://docs.hammer-eda.org/en/latest/index.html>`__.
For more information about Hammer's underlying implementation, visit the `Hammer documentation website <https://hammer-vlsi.readthedocs.io/en/latest/index.html>`__.
For details about the plugins used in this tutorial, check out the `OpenROAD tool plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/par/openroad>`__
and `Sky130 tech plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/sky130>`__.
For details about the plugins used in this tutorial, check out the `OpenROAD tool plugin repo + README <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__
and `Sky130 tech plugin repo + README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.

1
scripts/init-submodules-no-riscv-tools-nolog.sh
View File

@@ -150,6 +150,5 @@ fi
cat << EOT >> env.sh
# line auto-generated by init-submodules-no-riscv-tools.sh
__DIR="$RDIR"
PATH=\$__DIR/bin:\$PATH
PATH=\$__DIR/software/firemarshal:\$PATH
EOT

14
scripts/init-vlsi.sh
View File

@@ -4,15 +4,25 @@
set -e
set -o pipefail
# Initialize HAMMER and CAD-plugins
git submodule update --init --recursive vlsi/hammer
# exit script if not in Chipyard conda env
if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
echo 'ERROR: Chipyard conda env not activated. Please source env.sh and run this script again.'
exit
fi
# Initialize HAMMER CAD-plugins
if [[ $1 != *openroad* ]] && [[ $2 != *openroad* ]]; then
git submodule update --init --recursive vlsi/hammer-cadence-plugins
pip install -e vlsi/hammer-cadence-plugins
git submodule update --init --recursive vlsi/hammer-synopsys-plugins
pip install -e vlsi/hammer-synopsys-plugins
git submodule update --init --recursive vlsi/hammer-mentor-plugins
pip install -e vlsi/hammer-mentor-plugins
fi
# Initialize HAMMER tech plugin
# And add tech plugin to conda dependencies
if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then
git submodule update --init --recursive vlsi/hammer-$1-plugin
pip install -e vlsi/hammer-$1-plugin
fi

82
scripts/split-bb-files.py Executable file
View File

@@ -0,0 +1,82 @@
#!/usr/bin/env python3
import json
import argparse
from collections import defaultdict
# Schema of *.f emitted by circt
"""
<gen-src-dir>/<long-name>/gen-collateral/SimUART.cc
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSource.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSink.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSource_1.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSink_1.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSource_2.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSink_2.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncResetSynchronizerShiftReg_w4_d3_i0.sv
"""
def bfs_collect_submodules(tree):
output = set()
q = [(tree['instance_name'], tree['module_name'], tree['instances'])]
while len(q) != 0:
front = q[0]
q.pop(0)
(inst, mod, child) = front
output.add(mod)
for c in child:
q.append((c['instance_name'], c['module_name'], c['instances']))
return output
def write_lines_to_file(lines, file_path):
with open(file_path, "w") as fp:
for line in lines:
fp.write("%s\n" % line)
if __name__ == "__main__":
parser = argparse.ArgumentParser(description='Create *.model.bb.f and *.top.bb.f blackbox filelists')
parser.add_argument('--in-bb-f', type=str, required=True, help='All blackbox files filelist (includes both MODEL/TOP files)')
parser.add_argument('--in-top-hrchy-json', type=str, required=True, help='List containing hierarchy of top modules (top-module-hierarchy.json)')
parser.add_argument('--in-anno-json', type=str, required=True, help='Anno. file with blackbox annotations')
parser.add_argument('--out-top-bb-f', type=str, required=True, help='List of blackbox files for TOP')
parser.add_argument('--out-model-bb-f', type=str, required=True, help='List of blackbox files for MODEL')
args = parser.parse_args()
# module_path -> list of bb paths (not fully resolved paths)
mod_bb_dict = defaultdict(list)
with open(args.in_anno_json, "r") as f:
anno_data = json.load(f)
for anno in anno_data:
if 'BlackBoxInlineAnno' in anno['class']:
mod_bb_dict[anno['target']].append(anno['name'])
if 'BlackBoxPathAnno' in anno['class']:
mod_bb_dict[anno['target']].append(anno['path'])
with open(args.in_top_hrchy_json) as ihj:
ihj_data = json.load(ihj)
top_inner_modules = bfs_collect_submodules(ihj_data)
with open(args.in_bb_f) as ibf:
lines = ibf.read().splitlines()
tbfs = set()
for mod_path, bb_files in mod_bb_dict.items():
leaf_mod = mod_path.split('.')[-1]
# if matched, add the fully resolved path to the top bb filelist
if leaf_mod in top_inner_modules:
for line in lines:
for bb_file in bb_files:
if bb_file in line:
tbfs.add(line)
# now tbfs should be complete (need to remove tbf files from original bb file for model bb)
mbfs = set()
for line in lines:
if not line in tbfs:
mbfs.add(line)
write_lines_to_file(tbfs, args.out_top_bb_f)
write_lines_to_file(mbfs, args.out_model_bb_f)

34
scripts/upgrade-vlsi.sh Executable file
View File

@@ -0,0 +1,34 @@
#!/usr/bin/env bash
# exit script if any command fails
set -e
set -o pipefail
# exit script if not in Chipyard conda env
if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
echo 'ERROR: Chipyard conda env not activated. Please source env.sh and run this script again.'
exit
fi
# Get hammer submodules
package_names=$(git ls-files --stage | grep 160000 | awk '$4 ~/vlsi\/hammer.*/ {print $4}')
package_list=(${package_names})
plen="${#package_list[@]}"
if [[ ${plen} -gt 0 ]]; then
for p in "${package_list[@]}"; do
cd ${p}
echo "Updating current directory: $PWD"
git checkout `basename "$(git rev-parse --abbrev-ref origin/HEAD)"`
git pull
cd - > /dev/null
git add ${p}
pip install -e ${p} --upgrade
done
fi
# Upgrade hammer-vlsi separately.
pip install hammer-vlsi --upgrade

2
tools/barstools

Submodule tools/barstools updated: b71c31e66e...9760528f1d

4
variables.mk
View File

@@ -182,6 +182,10 @@ MODEL_MODS_FILELIST ?= $(build_dir)/$(long_name).model.f
# list of all blackbox files (may be included in the top/model.f files)
# this has the build_dir appended
BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f
# top blackbox module files to include
TOP_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).top.bb.f
# model blackbox module files to include (not including top blackbox modules)
MODEL_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).model.bb.f
# all module files to include (top, model, bb included)
ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f

183
vlsi/Makefile
View File

@@ -21,8 +21,9 @@ include $(base_dir)/variables.mk
sim_name ?= vcs # needed for GenerateSimFiles, but is unused
tech_name ?= asap7
tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
$(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
$(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
$(shell python3 -c "import os, hammer.technology.$(tech_name);\
print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\
$(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/$(tech_name))
SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
@@ -34,15 +35,14 @@ else
endif
ENV_YML ?= $(vlsi_dir)/env.yml
TECH_CONF ?= $(if $(filter $(tech_name),asap7), example-asap7.yml,\
example-sky130.yml)
TECH_CONF ?= example-$(tech_name).yml
TOOLS_CONF ?= example-tools.yml
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF)
HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
./example-vlsi-sky130,\
./example-vlsi)
VLSI_TOP ?= $(TOP)
VLSI_HARNESS_DUT_NAME ?= chiptop
VLSI_MODEL_DUT_NAME ?= chiptop
# If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),)
@@ -54,28 +54,37 @@ endif
#########################################################################################
# general rules
#########################################################################################
ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
extra_v_includes = $(build_dir)/EICG_wrapper.v
ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG)
VLSI_BB = /dev/null
else
VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
VLSI_BB = $(sim_top_blackboxes)
endif
.PHONY: default verilog
.PHONY: default
default: all
all: drc lvs
verilog: $(ALL_RTL)
#########################################################################################
# import other necessary rules and variables
#########################################################################################
include $(base_dir)/common.mk
#########################################################################################
# process RTL
#########################################################################################
VLSI_RTL = $(build_dir)/syn.f
ifneq ($(CUSTOM_VLOG), )
RTL_DEPS = $(CUSTOM_VLOG)
else
RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(TOP_SMEMS_FILE)
endif
$(VLSI_RTL): $(RTL_DEPS)
ifneq ($(CUSTOM_VLOG), )
> $(VLSI_RTL)
$(foreach file,$^,echo $(file) >> $(VLSI_RTL))
else
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
endif
#########################################################################################
# srams
#########################################################################################
@@ -100,7 +109,25 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
cd $(vlsi_dir) && cp output.json $@
#########################################################################################
# simulation input configuration
# synthesis input configuration
#########################################################################################
SYN_CONF = $(OBJ_DIR)/inputs.yml
GENERATED_CONFS = $(SYN_CONF)
ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(SRAM_CONF)
endif
$(SYN_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
for x in $(shell cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \
done
#########################################################################################
# simulation and power input configuration
#########################################################################################
include $(base_dir)/vcs.mk
@@ -116,127 +143,9 @@ $(sim_files): $(SIM_FILE_REQS) | $(build_dir)
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
include $(vlsi_dir)/sim.mk
$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@
for x in $(VCS_NONCC_OPTS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " options_meta: 'append'" >> $@
echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " defines_meta: 'append'" >> $@
echo " compiler_cc_opts:" >> $@
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_cc_opts_meta: 'append'" >> $@
echo " compiler_ld_opts:" >> $@
for x in $(filter-out "",$(VCS_LDFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_ld_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags:" >> $@
for x in $(SIM_FLAGS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@
endif
echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
else
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
endif
$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@
POWER_CONF = $(OBJ_DIR)/power-inputs.yml
include $(vlsi_dir)/power.mk
$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "power.inputs:" > $@
echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
ifneq ($(BINARY), )
echo " waveforms: [" >> $@
ifndef USE_VPD
echo " '$(sim_out_name).fsdb'" >> $@
else
echo " '$(sim_out_name).vpd'" >> $@
endif
echo " ]" >> $@
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
#########################################################################################
# synthesis input configuration
#########################################################################################
SYN_CONF = $(OBJ_DIR)/inputs.yml
GENERATED_CONFS = $(SYN_CONF)
ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(SRAM_CONF)
endif
$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " input_files:" >> $@
for x in $(VLSI_RTL); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
echo ' - "'$$x'"' >> $@; \
done
#########################################################################################
# AUTO BUILD FLOW

7
vlsi/example-asap7.yml
View File

@@ -1,6 +1,6 @@
# Technology Setup
# Technology used is ASAP7
vlsi.core.technology: asap7
vlsi.core.technology: "hammer.technology.asap7"
# Specify dir with ASAP7 Calibre deck tarball
technology.asap7.tarball_dir: "/path/to/asap7"
# Specify PDK and std cell install directories
@@ -94,7 +94,4 @@ vlsi.inputs.pin.assignments: [
]
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/asap7"]
vlsi.core.sram_generator_tool_path_meta: "append"
vlsi.core.sram_generator_tool: "hammer.technology.asap7.sram_compiler"

30
vlsi/example-openroad.yml
View File

@@ -1,22 +1,10 @@
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
# Yosys options
vlsi.core.synthesis_tool: "yosys"
vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
# Innovus options
vlsi.core.par_tool: "openroad"
vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"]
vlsi.core.par_tool_path_meta: "append"
# Magic options
vlsi.core.drc_tool: "magic"
vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"]
drc.magic.magic_bin: "magic"
# Netgen options
vlsi.core.lvs_tool: "netgen"
vlsi.core.lvs_tool_path: ["hammer/src/hammer-vlsi/lvs"]
vlsi.core.build_system: make
# Yosys
vlsi.core.synthesis_tool: "hammer.synthesis.yosys"
# OpenROAD
vlsi.core.par_tool: "hammer.par.openroad"
# Magic
vlsi.core.drc_tool: "hammer.drc.magic"
# Netgen
vlsi.core.lvs_tool: "hammer.lvs.netgen"

7
vlsi/example-sky130.yml
View File

@@ -1,6 +1,6 @@
# Technology Setup
# Technology used is Sky130
vlsi.core.technology: sky130
vlsi.core.technology: "hammer.technology.sky130"
vlsi.core.max_threads: 12
@@ -71,7 +71,4 @@ vlsi.inputs.pin.assignments: [
]
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"]
vlsi.core.sram_generator_tool_path_meta: "append"
vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"

4
vlsi/example-tech.yml
View File

@@ -1,7 +1,5 @@
# Technology Setup
vlsi.core.technology: <tech_name>
vlsi.core.technology_path: ["hammer-<tech_name>-plugin"]
vlsi.core.technology_path_meta: append
vlsi.core.technology: "hammer.technology.<tech_name>"
# technology files installation directory
technology.<tech_name>.install_dir: "</path/to/technology/pdk/>"

41
vlsi/example-tools.yml
View File

@@ -1,36 +1,23 @@
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
vlsi.core.build_system: make
# Genus options
vlsi.core.synthesis_tool: "genus"
vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
synthesis.genus.version: "1813"
vlsi.core.synthesis_tool: "hammer.synthesis.genus"
synthesis.genus.version: "211"
# Innovus options
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "191_ISR3"
vlsi.core.par_tool: "hammer.par.innovus"
par.innovus.version: "211"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options
vlsi.core.drc_tool: "calibre"
vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
drc.calibre.version: "2017.3_38.30"
vlsi.core.lvs_tool: "calibre"
vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
lvs.calibre.version: "2017.3_38.30"
vlsi.core.drc_tool: "hammer.drc.calibre"
drc.calibre.version: "2022.2_24.16"
vlsi.core.lvs_tool: "hammer.lvs.calibre"
lvs.calibre.version: "2022.2_24.16"
# VCS options
vlsi.core.sim_tool: "vcs"
vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
sim.vcs.version: "P-2019.06-SP2-5"
vlsi.core.sim_tool: "hammer.sim.vcs"
sim.vcs.version: "S-2021.09-SP1-1"
# Voltus options
vlsi.core.power_tool: "voltus"
vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
vlsi.core.power_tool_path_meta: "append"
power.voltus.version: "191_ISR3"
vlsi.core.power_tool: "hammer.power.voltus"
power.joules.version: "211"
power.voltus.version: "211_ISR3"
# NOTE (about VCS+Voltus versions): if using FSDB, the VCS version should be approx 2 years older than the Voltus version for compatibility

17
vlsi/example-vlsi
View File

@@ -5,12 +5,11 @@
import os
import hammer_vlsi
from hammer_vlsi import CLIDriver, HammerToolHookAction
from hammer.vlsi import CLIDriver, HammerTool, HammerToolHookAction
from typing import Dict, Callable, Optional, List
def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
def example_place_tap_cells(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
@@ -18,7 +17,7 @@ def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
def example_add_fillers(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
@@ -26,7 +25,7 @@ def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
def example_tool_settings(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
@@ -43,16 +42,16 @@ class ExampleDriver(CLIDriver):
# make_pre_insertion_hook will execute the custom hook before the specified step
# SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# make_post_insertion_hook will execute the custom hook after the specified step
# hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# make_replacement_hook will replace the specified step with a custom hook
# hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# make_removal_hook will remove the specified step from the flow
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
HammerTool.make_removal_hook("place_bumps"),
# The target step in any of the above calls may be a default step or another one of your custom hooks
]

19
vlsi/example-vlsi-sky130
View File

@@ -4,14 +4,13 @@
import os
import hammer_vlsi
from hammer_vlsi import CLIDriver, HammerToolHookAction
from hammer.vlsi import CLIDriver, HammerTool, HammerToolHookAction
from typing import Dict, Callable, Optional, List
from technology.sky130 import SKY130Tech
from hammer.technology.sky130 import SKY130Tech
def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
def example_place_tap_cells(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "sky130":
x.append('''
# TODO
@@ -19,7 +18,7 @@ def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
def example_add_fillers(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "sky130":
x.append('''
# TODO
@@ -27,7 +26,7 @@ def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
def example_tool_settings(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "sky130":
x.append('''
# TODO
@@ -45,16 +44,16 @@ class ExampleDriver(CLIDriver):
# make_pre_insertion_hook will execute the custom hook before the specified step
# SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# make_post_insertion_hook will execute the custom hook after the specified step
# hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# make_replacement_hook will replace the specified step with a custom hook
# hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# make_removal_hook will remove the specified step from the flow
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
HammerTool.make_removal_hook("place_bumps"),
# The target step in any of the above calls may be a default step or another one of your custom hooks
]

1
vlsi/hammer

Submodule vlsi/hammer deleted from 41105f964f

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: 80f0e276cf...f9e323bd64

2
vlsi/hammer-mentor-plugins

Submodule vlsi/hammer-mentor-plugins updated: 67f57f1200...eca060af45

2
vlsi/hammer-synopsys-plugins

Submodule vlsi/hammer-synopsys-plugins updated: 7f9ae30eb4...e53fa5c51f

85
vlsi/power.mk
View File

@@ -1,10 +1,75 @@
.PHONY: $(POWER_CONF)
power-par: $(POWER_CONF) sim-par-debug
power-par-$(VLSI_TOP): $(POWER_CONF) sim-par-debug-$(VLSI_TOP)
power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
redo-power-par: $(POWER_CONF)
redo-power-par-$(VLSI_TOP): $(POWER_CONF)
redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
$(OBJ_DIR)/power-par-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)
POWER_CONF = $(OBJ_DIR)/power-inputs.yml
POWER_RTL_CONF = $(OBJ_DIR)/power-rtl-inputs.yml
POWER_SYN_CONF = $(OBJ_DIR)/power-syn-inputs.yml
POWER_PAR_CONF = $(OBJ_DIR)/power-par-inputs.yml
.PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF)
$(POWER_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "power.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: TestDriver" >> $@
echo " tb_dut: 'testHarness/$(VLSI_MODEL_DUT_NAME)'" >> $@
ifneq ($(BINARY), )
echo " waveforms: [" >> $@
ifndef USE_VPD
echo " '$(sim_out_name).fsdb'" >> $@
else
echo " '$(sim_out_name).vpd'" >> $@
endif
echo " ]" >> $@
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
$(POWER_RTL_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.joules" > $@
echo "power.inputs:" >> $@
echo " level: rtl" >> $@
echo " input_files:" >> $@
for x in $(shell cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \
done
$(POWER_SYN_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.joules" > $@
echo "power.inputs:" >> $@
echo " level: syn" >> $@
$(POWER_PAR_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.voltus" > $@
echo "power.inputs:" >> $@
echo " level: par" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
power-rtl: $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug
power-rtl-$(VLSI_TOP): $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug-$(VLSI_TOP)
power-rtl: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
power-rtl-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
redo-power-rtl: $(POWER_CONF) $(POWER_RTL_CONF)
redo-power-rtl-$(VLSI_TOP): $(POWER_CONF) $(POWER_RTL_CONF)
redo-power-rtl: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
redo-power-rtl-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
power-syn: $(POWER_CONF) $(POWER_SYN_CONF) sim-syn-debug
power-syn-$(VLSI_TOP): $(POWER_CONF) $(POWER_SYN_CONF) sim-syn-debug-$(VLSI_TOP)
power-syn: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
power-syn-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
redo-power-syn: $(POWER_CONF) $(POWER_SYN_CONF)
redo-power-syn-$(VLSI_TOP): $(POWER_CONF) $(POWER_SYN_CONF)
redo-power-syn: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
redo-power-syn-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
power-par: $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug
power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug-$(VLSI_TOP)
power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
redo-power-par: $(POWER_CONF) $(POWER_PAR_CONF)
redo-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_CONF)
redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
$(OBJ_DIR)/power-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)

78
vlsi/sim.mk
View File

@@ -1,4 +1,82 @@
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF)
$(SIM_CONF): $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $(shell cat $(sim_common_files)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@
for x in $(filter-out -f $(sim_common_files),$(VCS_NONCC_OPTS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " options_meta: 'append'" >> $@
echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " defines_meta: 'append'" >> $@
echo " compiler_cc_opts:" >> $@
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_cc_opts_meta: 'append'" >> $@
echo " compiler_ld_opts:" >> $@
for x in $(filter-out "",$(VCS_LDFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_ld_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags:" >> $@
for x in $(SIM_FLAGS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@
endif
echo " tb_dut: 'TestDriver.testHarness.$(VLSI_MODEL_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(sim_common_files)
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
else
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
endif
$(SIM_TIMING_CONF): $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@
# Update hammer top-level sim targets to include our generated sim configs
redo-sim-rtl: $(SIM_CONF)
redo-sim-rtl-$(VLSI_TOP): $(SIM_CONF)

2
vlsi/tutorial.mk
View File

@@ -33,4 +33,6 @@ ifeq ($(tutorial),sky130-openroad)
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
VLSI_OBJ_DIR ?= build-sky130-openroad
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_CUSTOM_FIRRTL_PASS = 1
endif