Deduplicate across Chiypard configs into a ChipyardBaseConfig
This commit is contained in:
Jerry Zhao
@@ -8,7 +8,7 @@ Creating a Rocket and BOOM System
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-------------------------------------------
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Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific config fragments.
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Both BOOM and Rocket have config fragments labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_.
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Both BOOM and Rocket have config fragments labelled ``WithN{Small|Medium|Large|etc.}BoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_.
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When used together you can create a heterogeneous system.
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The following example shows a dual core BOOM with a single core Rocket.
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@@ -18,52 +18,6 @@ The following example shows a dual core BOOM with a single core Rocket.
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:start-after: DOC include start: DualBoomAndRocket
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:end-before: DOC include end: DualBoomAndRocket
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In this example, the ``WithNBoomCores`` and ``WithNBigCores`` config fragments set up the default parameters for the multiple BOOM and Rocket cores, respectively.
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However, for BOOM, an extra config fragment called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters.
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This config fragment applies to all BOOM cores in the system and changes the parameters for each.
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Great! Now you have a heterogeneous setup with BOOMs and Rockets.
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The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core).
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The ``WithRenumberHarts`` config fragment solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first).
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The reason this is needed is because by default the ``WithN...Cores(X)`` config fragment assumes that there are only BOOM or only Rocket cores in the system.
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Thus, without the ``WithRenumberHarts`` config fragment, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``.
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Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core.
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The config fragment to add to your system would look something like the following.
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.. code-block:: scala
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// create 6 cores (4 boom and 2 rocket)
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class WithHeterCoresSetup extends Config((site, here, up) => {
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case BoomTilesKey => {
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val boomTile0 = BoomTileParams(...) // params for boom core 0
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val boomTile1 = BoomTileParams(...) // params for boom core 1
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val boomTile2 = BoomTileParams(...) // params for boom core 2
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val boomTile3 = BoomTileParams(...) // params for boom core 3
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Seq(boomTile0, boomTile1, boomTile2, boomTile3)
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}
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case RocketTilesKey => {
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val rocketTile0 = RocketTileParams(...) // params for rocket core 0
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val rocketTile1 = RocketTileParams(...) // params for rocket core 1
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Seq(rocketTile0, rocketTile1)
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}
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})
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Then you could use this new config fragment like the following.
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.. code-block:: scala
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class SixCoreConfig extends Config(
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new WithTSI ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new WithHeterCoresSetup ++
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new freechips.rocketchip.system.BaseConfig)
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Note, in this setup you need to specify the ``hartId`` of each core in the "TileParams", where each ``hartId`` is unique.
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Adding Hwachas
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-------------------------------------------
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@@ -92,8 +46,7 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a
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:start-after: DOC include start: DualBoomAndRocketOneHwacha
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:end-before: DOC include end: DualBoomAndRocketOneHwacha
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In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores.
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Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core).
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The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core).
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Finally, the ``WithMultiRoCC`` config fragment is called.
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This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
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This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.
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@@ -130,3 +130,16 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
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case other => other
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}
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})
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class WithRocketICacheScratchpad extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000))))
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}
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})
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class WithRocketDCacheScratchpad extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000))))
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}
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})
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@@ -0,0 +1,26 @@
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package chipyard.config
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import freechips.rocketchip.config.{Config}
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// --------------
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// Chipyard abstract ("base") configuration
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// NOTE: This configuration is NOT INSTANTIABLE, as it defines a empty system with no tiles
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// --------------
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class AbstractConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model
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new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
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new testchipip.WithTSI ++ // use testchipip serial offchip link
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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@@ -9,34 +9,11 @@ import freechips.rocketchip.config.{Config}
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// ---------------------
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class ArianeConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem
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new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
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new testchipip.WithTSI ++ // use testchipip serial offchip link
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new ariane.WithNArianeCores(1) ++ // single Ariane core
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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new ariane.WithNArianeCores(1) ++ // single Ariane core
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new chipyard.config.AbstractConfig)
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class dmiArianeConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithSimAXIMem ++
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new chipyard.iobinders.WithTiedOffSerial ++
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new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new ariane.WithNArianeCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new chipyard.iobinders.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial
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new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation, override default tie-off debug
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new ariane.WithNArianeCores(1) ++ // single Ariane core
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new chipyard.config.AbstractConfig)
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@@ -7,151 +7,40 @@ import freechips.rocketchip.config.{Config}
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// ---------------------
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class SmallBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem
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new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
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new testchipip.WithTSI ++ // use testchipip serial offchip link
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new boom.common.WithNSmallBooms(1) ++ // small boom config
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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new chipyard.config.AbstractConfig)
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class MediumBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new boom.common.WithNMediumBooms(1) ++ // medium boom config
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new boom.common.WithNMediumBooms(1) ++ // medium boom config
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new chipyard.config.AbstractConfig)
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class LargeBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new boom.common.WithNLargeBooms(1) ++ // large boom config
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new chipyard.config.AbstractConfig)
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class MegaBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new boom.common.WithNMegaBooms(1) ++ // mega boom config
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new boom.common.WithBoomBranchPrintf ++
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new boom.common.WithNMegaBooms(1) ++ // mega boom config
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new chipyard.config.AbstractConfig)
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class DualSmallBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new boom.common.WithNSmallBooms(2) ++ // 2 boom cores
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new boom.common.WithNSmallBooms(2) ++ // 2 boom cores
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new chipyard.config.AbstractConfig)
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class HwachaLargeBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new boom.common.WithNLargeBooms(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new chipyard.config.AbstractConfig)
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class LoopbackNICLargeBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback
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new testchipip.WithTSI ++
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new icenet.WithIceNIC ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback
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new icenet.WithIceNIC ++ // build a NIC
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new boom.common.WithNLargeBooms(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new chipyard.config.AbstractConfig)
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class DromajoBoomConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo
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new testchipip.WithTSI ++
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new chipyard.config.WithTraceIO ++ // enable the traceio
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new boom.common.WithNSmallBooms(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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new chipyard.config.AbstractConfig)
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||||
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||||
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@@ -7,108 +7,38 @@ import freechips.rocketchip.config.{Config}
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// ---------------------
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||||
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class LargeBoomAndRocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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||||
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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||||
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem
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||||
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
|
||||
new testchipip.WithTSI ++ // use testchipip serial offchip link
|
||||
new chipyard.config.WithBootROM ++ // use default bootrom
|
||||
new chipyard.config.WithUART ++ // add a UART
|
||||
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
|
||||
new boom.common.WithNLargeBooms(1) ++ // single-core boom
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
|
||||
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: BoomAndRocketWithHwacha
|
||||
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
|
||||
new boom.common.WithNLargeBooms(1) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
|
||||
new boom.common.WithNLargeBooms(1) ++ // add 1 boom core
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: BoomAndRocketWithHwacha
|
||||
// DOC include start: DualBoomAndRocketOneHwacha
|
||||
|
||||
// DOC include start: DualBoomAndRocketOneHwacha
|
||||
class LargeBoomAndHwachaRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
|
||||
new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-1 (rocket)
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new boom.common.WithNLargeBooms(1) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
|
||||
new boom.common.WithNLargeBooms(1) ++ // add 1 boom core
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: DualBoomAndRocketOneHwacha
|
||||
|
||||
|
||||
// DOC include start: DualBoomAndRocket
|
||||
class DualLargeBoomAndDualRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new boom.common.WithNLargeBooms(2) ++ // 2 boom cores
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // add 2 rocket cores
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: DualBoomAndRocket
|
||||
|
||||
class LargeBoomAndRocketWithControlCoreConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core
|
||||
new boom.common.WithNLargeBooms(1) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
|
||||
new boom.common.WithNLargeBooms(1) ++ // Add 1 boom core
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
@@ -7,556 +7,179 @@ import freechips.rocketchip.config.{Config}
|
||||
// --------------
|
||||
|
||||
class RocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model
|
||||
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
|
||||
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
|
||||
new testchipip.WithTSI ++ // use testchipip serial offchip link
|
||||
new chipyard.config.WithBootROM ++ // use default bootrom
|
||||
new chipyard.config.WithUART ++ // add a UART
|
||||
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
|
||||
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class HwachaRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: GemminiRocketConfig
|
||||
class GemminiRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: GemminiRocketConfig
|
||||
|
||||
class RoccRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
// DOC include start: JtagRocket
|
||||
class jtagRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new chipyard.iobinders.WithSimDebug ++ // add SimDebug, in addition to default SimSerial
|
||||
new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: JtagRocket
|
||||
|
||||
// DOC include start: DmiRocket
|
||||
class dmiRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffSerial ++
|
||||
new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new chipyard.iobinders.WithTiedOffSerial ++ // tie-off serial, override default add SimSerial
|
||||
new chipyard.iobinders.WithSimDebug ++ // add SimDebug, override default tie-off debug
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: DmiRocket
|
||||
|
||||
// DOC include start: GCDTLRocketConfig
|
||||
class GCDTLRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: GCDTLRocketConfig
|
||||
|
||||
// DOC include start: GCDAXI4BlackBoxRocketConfig
|
||||
class GCDAXI4BlackBoxRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: GCDAXI4BlackBoxRocketConfig
|
||||
|
||||
class LargeSPIFlashROMRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class SmallSPIFlashRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable)
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB)
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class SimAXIRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class SimBlockDeviceRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
|
||||
new testchipip.WithTSI ++
|
||||
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class BlockDeviceModelRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel
|
||||
new testchipip.WithTSI ++
|
||||
new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: GPIORocketConfig
|
||||
class GPIORocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: GPIORocketConfig
|
||||
|
||||
class QuadRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class RV32RocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class GB1MemoryRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: Sha3Rocket
|
||||
class Sha3RocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: Sha3Rocket
|
||||
|
||||
// DOC include start: InitZeroRocketConfig
|
||||
class InitZeroRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: InitZeroRocketConfig
|
||||
|
||||
class LoopbackNICRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback
|
||||
new testchipip.WithTSI ++
|
||||
new icenet.WithIceNIC ++ // add an IceNIC
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: l1scratchpadrocket
|
||||
class L1ScratchpadSmallRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
class ScratchpadOnlyRocketConfig extends Config(
|
||||
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
|
||||
new freechips.rocketchip.subsystem.WithNBanks(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMemPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: l1scratchpadrocket
|
||||
|
||||
class L1ScratchpadRocketConfig extends Config(
|
||||
new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad
|
||||
new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: mbusscratchpadrocket
|
||||
class MbusScratchpadRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: mbusscratchpadrocket
|
||||
|
||||
// DOC include start: RingSystemBusRocket
|
||||
class RingSystemBusRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new testchipip.WithRingSystemBus ++ // Ring-topology system bus
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: RingSystemBusRocket
|
||||
|
||||
class StreamingPassthroughRocketConfig extends Config(
|
||||
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// DOC include start: StreamingFIRRocketConfig
|
||||
class StreamingFIRRocketConfig extends Config (
|
||||
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: StreamingFIRRocketConfig
|
||||
|
||||
class SmallNVDLARocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class LargeNVDLARocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class MMIORocketConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTAdapter ++
|
||||
new chipyard.iobinders.WithTieOffInterrupts ++
|
||||
new chipyard.iobinders.WithBlackBoxSimMem ++
|
||||
new chipyard.iobinders.WithTiedOffDebug ++
|
||||
new chipyard.iobinders.WithSimSerial ++
|
||||
new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port
|
||||
new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port
|
||||
new testchipip.WithTSI ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
|
||||
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
|
||||
index f29c580..0bd36ca 100644
|
||||
index 8e6e486..fc3a811 100644
|
||||
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
|
||||
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
|
||||
@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config(
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithUART ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
@@ -105,7 +105,7 @@ class GB1MemoryRocketConfig extends Config(
|
||||
|
||||
// DOC include start: Sha3Rocket
|
||||
class Sha3RocketConfig extends Config(
|
||||
- new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
|
||||
+// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: Sha3Rocket
|
||||
|
||||
Reference in New Issue
Block a user