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Bump testchipip for improved TLSerdesser

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This commit is contained in:
Jerry Zhao
2024-01-26 17:52:08 -08:00
parent 150f888a62
commit 66deeee9a7
7 changed files with 29 additions and 29 deletions
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2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -70,7 +70,7 @@ class AbstractConfig extends Config(
new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
)
)) ++
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad

6
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config(
isMemoryDevice = true
)),
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock
))) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
@@ -77,8 +77,8 @@ class ChipBringupHostConfig extends Config(
size = BigInt("80000000", 16)
))
)),
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
))) ++
//============================

4
generators/chipyard/src/main/scala/config/ChipletConfigs.scala
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@@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config(
new testchipip.serdes.WithSerialTL(Seq(
testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga
client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client
phyParams = testchipip.serdes.ExternalSyncSerialParams() // bringup serial-tl is sync'd to external clock
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock
),
testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client
@@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config(
)),
slaveWhere = OBUS
)),
phyParams = testchipip.serdes.SourceSyncSerialParams() // chip-to-chip serial-tl is symmetric source-sync'd
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
))
) ++
new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory

10
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
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@@ -47,16 +47,16 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// Figure out which clock drives the harness TLSerdes, based on the port type
val serial_ram_clock = dut.serial_tl_pad match {
case io: InternalSyncSerialIO => io.clock_out
case io: ExternalSyncSerialIO => clock
case io: InternalSyncPhitIO => io.clock_out
case io: ExternalSyncPhitIO => clock
}
dut.serial_tl_pad match {
case io: ExternalSyncSerialIO => io.clock_in := clock
case io: InternalSyncSerialIO =>
case io: ExternalSyncPhitIO => io.clock_in := clock
case io: InternalSyncPhitIO =>
}
dut.serial_tl_pad match {
case pad: DecoupledSerialIO => {
case pad: DecoupledPhitIO => {
withClockAndReset(serial_ram_clock, reset) {
// SerialRAM implements the memory regions the chip expects
val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)

20
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -209,17 +209,17 @@ class WithTiedOffDMI extends HarnessBinder({
class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
port.io match {
case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
case io: SourceSyncSerialIO => {
case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
case io: SourceSyncPhitIO => {
io.clock_in := false.B.asClock
io.reset_in := false.B.asAsyncReset
io.in := DontCare
io.phit_in := DontCare
io.credit_in := DontCare
}
}
port.io match {
case io: InternalSyncSerialIO =>
case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
case io: InternalSyncPhitIO =>
case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock
case _ =>
}
}
@@ -228,17 +228,17 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
class WithSimTSIOverSerialTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
port.io match {
case io: InternalSyncSerialIO =>
case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
case io: InternalSyncPhitIO =>
case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock
}
port.io match {
case io: DecoupledSerialIO => {
case io: DecoupledPhitIO => {
// If the port is locally synchronous (provides a clock), drive everything with that clock
// Else, drive everything with the harnes clock
val clock = port.io match {
case io: InternalSyncSerialIO => io.clock_out
case io: ExternalSyncSerialIO => th.harnessBinderClock
case io: InternalSyncPhitIO => io.clock_out
case io: ExternalSyncPhitIO => th.harnessBinderClock
}
withClock(clock) {
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)

14
generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
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@@ -59,25 +59,25 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
(p0: SerialTLPort) => p0.portId == chip0portId,
(p1: SerialTLPort) => p1.portId == chip1portId,
(th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = {
def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = {
clkSink.clock_in := clkSource.clock_out
clkSink.in <> clkSource.out
clkSource.in <> clkSink.out
}
def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = {
a.clock_in := b.clock_out
b.clock_in := a.clock_out
a.reset_in := b.reset_out
b.reset_in := a.reset_out
a.in := b.out
b.in := a.out
a.phit_in := b.phit_out
b.phit_in := a.phit_out
a.credit_in := b.credit_out
b.credit_in := a.credit_out
}
(p0.io, p1.io) match {
case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
case (io0: SourceSyncSerialIO , io1: SourceSyncSerialIO ) => connectSourceSyncSerialIO (io0, io1)
case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)
case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0)
case (io0: SourceSyncPhitIO , io1: SourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1)
}
}
)

2
generators/testchipip

Submodule generators/testchipip updated: edacb214f0...2e9eb79f9b