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Fix vc707 clock freqs

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This commit is contained in:
Jerry Zhao
2023-10-31 21:40:45 -07:00
parent 52215f3d40
commit 6bb173bd21
1 changed files with 7 additions and 2 deletions
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9
fpga/src/main/scala/vc707/Configs.scala
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@@ -45,6 +45,8 @@ class WithVC707Tweaks extends Config (
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq
@@ -74,8 +76,11 @@ class BoomVC707Config extends Config (
)
class WithFPGAFrequency(fMHz: Double) extends Config (
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
new chipyard.config.WithMemoryBusFrequency(fMHz)
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
new chipyard.config.WithControlBusFrequency(fMHz) ++
new chipyard.config.WithFrontBusFrequency(fMHz)
)
class WithFPGAFreq25MHz extends WithFPGAFrequency(25)