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[docs][ci skip] Remove extra backticks in docs (#312)

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Closes #299
This commit is contained in:
harrisonliew
2019-10-16 10:43:55 -07:00
committed by GitHub
parent c308985ae2 b0b6466c22
commit 701129fb62
2 changed files with 10 additions and 6 deletions
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10
docs/VLSI/Tutorial.rst
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@@ -64,7 +64,7 @@ In the Chipyard root, run:
.. code-block:: shell
``./scripts/init-vlsi.sh asap7``
./scripts/init-vlsi.sh asap7
to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
@@ -84,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u
make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches).
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). This change is automatically inferred by the makefile but is included here for completeness.
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.
@@ -111,7 +111,7 @@ Synthesis
^^^^^^^^^
.. code-block:: shell
``make syn``
make syn
Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
@@ -119,7 +119,7 @@ Place-and-Route
^^^^^^^^^^^^^^^
.. code-block:: shell
``make par``
make par
After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
@@ -131,7 +131,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped
.. code-block:: shell
``python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds``
python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds
By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names.

6
vlsi/Makefile
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@@ -23,7 +23,11 @@ tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src
SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
ifeq ($(tech_name),asap7)
MACROCOMPILER_MODE ?= --mode synflops
else
MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
endif
OBJ_DIR ?= $(vlsi_dir)/build
ENV_YML ?= $(vlsi_dir)/env.yml
INPUT_CONFS ?= example.yml