minor formatting fixes, changing name from Tutorial to ASAP7-Tutorial
This commit is contained in:
nayiri-k
@@ -9,40 +9,40 @@ Project Structure
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This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
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* Makefile, sim.mk, power.mk
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* ``Makefile``, ``sim.mk``, ``power.mk``
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* Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
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* build
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* ``build``
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* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
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* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
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* env.yml
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* ``env.yml``
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* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
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* example-vlsi
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* ``example-vlsi``
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* Entry point to Hammer. Contains example placeholders for hooks.
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* example-asap7.yml, example-tools.yml
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* ``example-asap7.yml``, ``example-tools.yml``
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* Hammer IR for this tutorial.
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* example-design.yml, example-nangate45.yml, example-tech.yml
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* ``example-design.yml``, ``example-nangate45.yml``, ``example-tech.yml``
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* Hammer IR not used for this tutorial but provided as templates.
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* generated-src
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* ``generated-src``
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* All of the elaborated Chisel and FIRRTL.
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* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
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* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
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* Core, tool, tech repositories.
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* view_gds.py
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* ``view_gds.py``
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* A convenience script to view a layout using gdstk or gdspy. Only use this for small layouts (i.e. smaller than the TinyRocketConfig example) since the gdstk-produced SVG will be too big and gdspy's GUI is very slow for large layouts!
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@@ -65,7 +65,7 @@ In the Chipyard root, run:
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./scripts/init-vlsi.sh asap7
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to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
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to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
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Pull the Hammer environment into the shell:
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@@ -106,7 +106,7 @@ Synthesis
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make syn CONFIG=TinyRocketConfig
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Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
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Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw quality of results data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a work in progress.
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Place-and-Route
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^^^^^^^^^^^^^^^
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@@ -144,15 +144,15 @@ Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not h
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Simulation
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^^^^^^^^^^
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Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation:
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Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and post-P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation:
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.. code-block:: shell
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make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple
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Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` targets, respectively.
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Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
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You can also append ``-debug`` and ``-debug-timing`` to the above sim targets, which will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
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Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
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Power/Rail Analysis
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^^^^^^^^^^^^^^^^^^^
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@@ -164,4 +164,4 @@ Post-P&R power and rail (IR drop) analysis is supported with Voltus:
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If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim-<syn/par>-debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform.
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Note that power and rail analysis can also be run without gate-level simulation, but you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Only static and active (vectorless) power & IR drop will be reported.
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To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported.
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@@ -49,6 +49,6 @@ Running the VLSI tool flow
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--------------------------
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For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
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For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/Tutorial:ASAP7 Tutorial`.
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For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`.
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@@ -9,36 +9,36 @@ Project Structure
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This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
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* Makefile, sim.mk, power.mk
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* ``Makefile``, ``sim.mk``, ``power.mk``
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* Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
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* build
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* ``build``
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* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
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* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
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* env.yml
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* ``env.yml``
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* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
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* example-vlsi-sky130
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* ``example-vlsi-sky130``
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* Entry point to Hammer. Contains example placeholders for hooks.
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* example-sky130.yml, example-tools.yml
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* ``example-sky130.yml``, ``example-tools.yml``
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* Hammer IR for this tutorial.
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* example-design.yml, example-nangate45.yml, example-tech.yml
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* ``example-design.yml``, ``example-nangate45.yml``, ``example-tech.yml``
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* Hammer IR not used for this tutorial but provided as templates.
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* generated-src
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* ``generated-src``
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* All of the elaborated Chisel and FIRRTL.
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* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
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* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
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* Core, tool, tech repositories.
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@@ -47,7 +47,7 @@ Prerequisites
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* Python 3.4+
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* numpy package
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* Genus, Innovus, and Calibre licenses
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* Genus, Innovus, Voltus, VCS, and Calibre licenses
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* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
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Initial Setup
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@@ -92,8 +92,8 @@ example-sky130.yml
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^^^^^^^^^^^^^^^^^^
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This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
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First, set ``technology.sky130.sky130A`` to the absolute path to the ``sky130A`` directory containing the Sky130 PDK files. See the
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`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/sky130sram/src/hammer-vlsi/technology/sky130/README.md>`__
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First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
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`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
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for details about the PDK setup.
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@@ -103,7 +103,7 @@ Synthesis
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make syn tech_name=sky130 CONFIG=TinyRocketConfig
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Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
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Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw quality of results data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a work in progress.
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Place-and-Route
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^^^^^^^^^^^^^^^
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@@ -11,6 +11,6 @@ In particular, we aim to support the Hammer physical design generator flow.
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Building-A-Chip
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Hammer
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Basic-Flow
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Tutorial
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ASAP7-Tutorial
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Sky130-Tutorial
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Advanced-Usage
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