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Merge branch 'graphics' of https://github.com/hansungk/chipyard into graphics

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This commit is contained in:
Richard Yan
2024-07-21 00:03:04 -07:00
parent 8518e33831 9d0f02e34e
commit 749b61d4b9
71 changed files with 510 additions and 194 deletions
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3
.github/scripts/check-commit.sh vendored
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@@ -45,7 +45,8 @@ search () {
done
}
submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc")
dir="generators"
branches=("master" "main" "dev")
search

4
.github/scripts/defaults.sh vendored
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@@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-gpu"]="chipyard-radiance chipyard-radiance-fuzzer chipyard-coalescer coalescer"
grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
@@ -42,6 +42,7 @@ declare -A mapping
mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig"
mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
mapping["chipyard-compressacc"]=" CONFIG=ZstdCompressorRocketConfig"
mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig"
mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
@@ -73,6 +74,7 @@ mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig"
mapping["chipyard-radiance"]=" CONFIG=RadianceConfig"
mapping["chipyard-radiance-fuzzer"]=" CONFIG=RadianceFuzzerConfig"
mapping["chipyard-coalescer"]=" CONFIG=MemtraceCoreConfig"

18
.github/scripts/run-tests.sh vendored
View File

@@ -72,7 +72,7 @@ case $1 in
run_bmark
;;
chipyard-prefetchers)
run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1
;;
rocketchip)
run_bmark
@@ -81,13 +81,17 @@ case $1 in
GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
cd $LOCAL_SIM_DIR
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal LOADMEM=1
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal LOADMEM=1
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal LOADMEM=1
;;
chipyard-mempress)
(cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv LOADMEM=1
;;
chipyard-compressacc)
(cd $LOCAL_CHIPYARD_DIR/generators/compress-acc/software-zstd/compress && ./build-hcb-single-file.sh)
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/compress-acc/software-zstd/compress/009987_cl0_ws12.riscv LOADMEM=1
;;
chipyard-manymmioaccels)
make -C $LOCAL_CHIPYARD_DIR/tests
@@ -127,6 +131,10 @@ case $1 in
make -C $LOCAL_CHIPYARD_DIR/tests
run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
;;
chipyard-rerocc)
make -C $LOCAL_CHIPYARD_DIR/generators/rerocc/tests
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/rerocc/tests/rerocc.riscv LOADMEM=1
;;
tracegen)
run_tracegen
;;

48
.github/workflows/chipyard-run-tests.yml vendored
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@@ -777,6 +777,29 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-llcchiplet"
chipyard-rerocc-run-tests:
name: chipyard-rerocc-run-tests
needs: prepare-chipyard-accels
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-rerocc"
chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
needs: prepare-chipyard-accels
@@ -869,6 +892,29 @@ jobs:
group-key: "group-accels"
project-key: "chipyard-mempress"
chipyard-compressacc-run-tests:
name: chipyard-compressacc-run-tests
needs: prepare-chipyard-accels
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-compressacc"
tracegen-boomv3-run-tests:
name: tracegen-boomv3-run-tests
@@ -1143,10 +1189,12 @@ jobs:
chipyard-tethered-run-tests,
chipyard-symmetric-run-tests,
chipyard-llcchiplet-run-tests,
chipyard-rerocc-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
chipyard-prefetchers-run-tests,
chipyard-mempress-run-tests,
chipyard-compressacc-run-tests,
chipyard-constellation-run-tests,
tracegen-boomv3-run-tests,
tracegen-boomv4-run-tests,

7
.gitmodules vendored
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@@ -151,7 +151,12 @@
[submodule "tools/midas-targetutils"]
path = tools/midas-targetutils
url = https://github.com/firesim/midas-targetutils.git
[submodule "generators/rerocc"]
path = generators/rerocc
url = https://github.com/ucb-bar/rerocc.git
[submodule "generators/compress-acc"]
path = generators/compress-acc
url = https://github.com/ucb-bar/compress-acc.git
[submodule "generators/radiance"]
path = generators/radiance
url = https://github.com/ucb-bar/radiance.git

21
build.sbt
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@@ -98,8 +98,8 @@ lazy val chisel6Settings = Seq(
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)
)
lazy val chisel3Settings = Seq(
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.1"),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.1" cross CrossVersion.full)
)
lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq(
@@ -172,8 +172,9 @@ val stageDir = if (chisel6) "tools/stage/src/main/scala" else "tools/stage-chise
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
dsptools, rocket_dsp_utils,
radiance, gemmini, icenet, tracegen, cva6, nvdla, radiance, sodor, ibex, fft_generator,
constellation, mempress, barf, shuttle, caliptra_aes)
radiance, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
compressacc)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(
libraryDependencies ++= Seq(
@@ -183,6 +184,11 @@ lazy val chipyard = (project in file("generators/chipyard"))
.settings(commonSettings)
.settings(Compile / unmanagedSourceDirectories += file(stageDir))
lazy val compressacc = (project in file("generators/compress-acc"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val mempress = (project in file("generators/mempress"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -264,6 +270,11 @@ lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val rerocc = (project in file("generators/rerocc"))
.dependsOn(rocketchip, constellation, boom)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -342,6 +353,6 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val fpga_platforms = (project in file("./fpga"))
lazy val chipyard_fpga = (project in file("./fpga"))
.dependsOn(chipyard, fpga_shells)
.settings(commonSettings)

51
common.mk
View File

@@ -22,7 +22,7 @@ HELP_COMPILATION_VARIABLES += \
" MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \
" ASPECTS = comma separated list of Chisel aspect flows to run (e.x. chipyard.upf.ChipTopUPFAspect)"
EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) $(ARGSROM_TARGETS)
EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS)
EXTRA_SIM_CXXFLAGS ?=
EXTRA_SIM_LDFLAGS ?=
EXTRA_SIM_SOURCES ?=
@@ -96,19 +96,9 @@ TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout)
TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT))
TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT))
# This assumes no SBT meta-build sources
SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools)
SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators tools)
SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties
#########################################################################################
# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change)
#########################################################################################
$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES)
ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP)))
cd $(base_dir) && $(SBT) "reload"
touch $@
else
cd $(base_dir) && $(SBT) "exit"
endif
#########################################################################################
# copy over bootrom files
@@ -122,13 +112,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
#########################################################################################
# compile scala jars
#########################################################################################
$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
$(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
$(CHECK_SUBMODULES_COMMAND)
mkdir -p $(dir $@)
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
$(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH))
# order only dependency between sbt runs needed to avoid concurrent sbt runs
$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(GENERATOR_CLASSPATH)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
@@ -136,9 +126,9 @@ $(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
# verilog generation pipeline
#########################################################################################
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(GENERATOR_CLASSPATH) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir)
(set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
(set -o pipefail && $(call run_jar_scala_main,$(GENERATOR_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
--target-dir $(build_dir) \
--name $(long_name) \
--top-module $(MODEL_PACKAGE).$(MODEL) \
@@ -182,7 +172,8 @@ SFC_MFC_TARGETS = \
$(MFC_MODEL_SMEMS_JSON) \
$(MFC_FILELIST) \
$(MFC_BB_MODS_FILELIST) \
$(GEN_COLLATERAL_DIR)
$(GEN_COLLATERAL_DIR) \
$(FIRTOOL_LOG_FILE)
MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
@@ -197,7 +188,7 @@ endif
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
rm -rf $(GEN_COLLATERAL_DIR)
firtool \
(set -o pipefail && firtool \
--format=fir \
--export-module-hierarchy \
--verify-each=true \
@@ -211,7 +202,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
--annotation-file=$(FINAL_ANNO_FILE) \
--split-verilog \
-o $(GEN_COLLATERAL_DIR) \
$(FIRRTL_FILE)
$(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE))
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
# DOC include end: FirrtlCompiler
@@ -221,6 +212,7 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
--model-hier-json $(MFC_MODEL_HRCHY_JSON) \
--top-hier-json $(MFC_TOP_HRCHY_JSON) \
--in-all-filelist $(MFC_FILELIST) \
--in-bb-filelist $(MFC_BB_MODS_FILELIST) \
--dut $(TOP) \
--model $(MODEL) \
--target-dir $(GEN_COLLATERAL_DIR) \
@@ -246,12 +238,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
TOP_MACROCOMPILER_MODE ?= --mode synflops
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(TOP_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR)
MODEL_MACROCOMPILER_MODE = --mode synflops
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF)
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(MODEL_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR)
@@ -350,7 +342,9 @@ run-binaries-fast: check-binaries $(addsuffix .run.fast,$(wildcard $(BINARIES)))
# run simulator with as much debug info as possible
run-binary-debug: check-binary $(BINARY).run.debug
run-binary-debug-bg: check-binary $(BINARY).run.debug.bg
run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES)))
run-binaries-debug-bg: check-binaries $(addsuffix .run.debug.bg,$(wildcard $(BINARIES)))
%.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
@@ -364,6 +358,19 @@ run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES)
$(BINARY_ARGS) \
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
%.run.debug.bg: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \
$(PERMISSIVE_ON) \
$(call get_common_sim_flags,$*) \
$(VERBOSE_FLAGS) \
$(call get_waveform_flag,$(call get_sim_out_name,$*)) \
$(PERMISSIVE_OFF) \
$* \
$(BINARY_ARGS) \
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) >$(call get_sim_out_name,$*).log \
& echo "PID=$$!")
run-fast: run-asm-tests-fast run-bmark-tests-fast
#########################################################################################

2
conda-reqs/chipyard-extended.yaml
View File

@@ -30,7 +30,7 @@ dependencies:
- bison
- flex
- expat
- python>=3.9
- python>=3.9,<3.11
- bc
- unzip
- patch

2
conda-reqs/circt.json
View File

@@ -1,3 +1,3 @@
{
"version": "firtool-1.66.0"
"version": "firtool-1.75.0"
}

6
docs/Generators/CompressAcc.rst Normal file
View File

@@ -0,0 +1,6 @@
CompressAcc
====================================
We have (de)compression accelerators for two major compression algorithms : Snappy(`Snappy Github <https://github.com/google/snappy>`__) and ZStd(`ZStd Github <https://github.com/facebook/zstd>`__).
For more information, check out the CDPU paper: `CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems <https://dl.acm.org/doi/abs/10.1145/3579371.3589074>`__ .

1
docs/Generators/index.rst
View File

@@ -33,4 +33,5 @@ so changes to the generators themselves will automatically be used when building
Sodor
Shuttle
Mempress
CompressAcc
Prefetchers

2
docs/Prototyping/General.rst
View File

@@ -30,7 +30,7 @@ For example:
# converts to
make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream
make SBT_PROJECT=chipyard_fpga MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream
Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``.
These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system.

10
fpga/Makefile
View File

@@ -17,7 +17,7 @@ sim_name := none
SUB_PROJECT ?= vcu118
ifeq ($(SUB_PROJECT),vc707)
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= VC707FPGATestHarness
VLOG_MODEL ?= VC707FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vc707
@@ -31,7 +31,7 @@ ifeq ($(SUB_PROJECT),vc707)
endif
ifeq ($(SUB_PROJECT),vcu118)
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= VCU118FPGATestHarness
VLOG_MODEL ?= VCU118FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vcu118
@@ -45,7 +45,7 @@ ifeq ($(SUB_PROJECT),vcu118)
endif
ifeq ($(SUB_PROJECT),nexysvideo)
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= NexysVideoHarness
VLOG_MODEL ?= NexysVideoHarness
MODEL_PACKAGE ?= chipyard.fpga.nexysvideo
@@ -60,7 +60,7 @@ endif
ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= Arty35THarness
VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty
@@ -74,7 +74,7 @@ ifeq ($(SUB_PROJECT),arty35t)
endif
ifeq ($(SUB_PROJECT),arty100t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= Arty100THarness
VLOG_MODEL ?= Arty100THarness
MODEL_PACKAGE ?= chipyard.fpga.arty100t

2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: 474ad19113...2d36b0ab43

3
fpga/src/main/scala/vc707/Configs.scala
View File

@@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
import freechips.rocketchip.tile.{XLen}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}

3
fpga/src/main/scala/vcu118/Configs.scala
View File

@@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
import freechips.rocketchip.tile.{XLen}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}

2
generators/boom

Submodule generators/boom updated: 506c11c99c...6a3ad0a1d9

1
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -41,6 +41,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators
{
override lazy val module = new DigitalTopModule(this)
}

2
generators/chipyard/src/main/scala/SpikeTile.scala
View File

@@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.prci._
case class SpikeCoreParams() extends CoreParams {
val useVM = true

34
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
View File

@@ -27,9 +27,9 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
@@ -72,7 +72,7 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr
}
}
})
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
@@ -102,6 +102,32 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
}
})
// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies
class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock"))
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
clockGroupsSourceNode.out.foreach { case (bundle, edge) =>
bundle.member.data.foreach { b =>
b.clock := clock_io
b.reset := reset_io
}
}
(Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
class WithClockTapIOCells extends OverrideIOBinder({
(system: CanHaveClockTap) => {
system.clockTapIO.map { tap =>

3
generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
View File

@@ -48,9 +48,10 @@ class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule
val name = combiners(i)._1
i = i + 1
require(g.size >= 1)
val names = g.map(_.name.getOrElse("unamed"))
val takes = g.map(_.take).flatten
require(takes.distinct.size <= 1,
s"Clock group $name has non-homogeneous requested ClockParameters $takes")
s"Clock group $name has non-homogeneous requested ClockParameters ${names.zip(takes)}")
require(takes.size > 0,
s"Clock group $name has no inheritable frequencies")
(grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r)

1
generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
View File

@@ -28,6 +28,7 @@ class ClockGroupParameterModifier(
sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { s => s })(
implicit p: Parameters, v: ValName) extends LazyModule {
val node = ClockGroupAdapterNode(sourceFn, sinkFn)
override def shouldBeInlined = true
lazy val module = new LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, _), (i, _)) =>
(o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD }

9
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
View File

@@ -37,9 +37,10 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLBuffer()
@@ -70,13 +71,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
}
val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get
clock_gater
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get
reset_setter
} }

2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
View File

@@ -59,6 +59,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithNICIOPunchthrough ++
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithGCDBusyPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++
@@ -122,7 +123,6 @@ class AbstractConfig extends Config(
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */
// ================================================
// Set up power, reset and clocking
// ================================================

34
generators/chipyard/src/main/scala/config/ClockingConfigs.scala Normal file
View File

@@ -0,0 +1,34 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{MBUS, SBUS}
import testchipip.soc.{OBUS}
//==================================================
// This file contains examples of the different ways
// clocks can be generated for chiypard designs
//==================================================
// The default constructs IOs for all requested clocks in the chiptopClockGroupsNode
// Note: This is what designs inheriting from AbstractConfig do by default
class DefaultClockingRocketConfig extends Config(
new chipyard.clocking.WithPassthroughClockGenerator ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// This is a more physically realistic approach, normally we can't punch out a separate
// pin for each clock domain. The standard "test chip" approach is to punch a few slow clock
// inputs, integrate a PLL, and generate an array of selectors/dividers to configure the
// clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info
class ChipLikeClockingRocketConfig extends Config(
new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single
// clock input pin.
class SingleClockBroadcastRocketConfig extends Config(
new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

2
generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
View File

@@ -1,7 +1,7 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.prci.AsynchronousCrossing
class MemtraceCoreConfig extends Config(
// Memtrace

1
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
View File

@@ -1,7 +1,6 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------
// Configs with MMIO accelerators

1
generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
View File

@@ -1,7 +1,6 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------------------------------------
// Configs which demonstrate modifying the uncore memory system

24
generators/chipyard/src/main/scala/config/NoCConfigs.scala
View File

@@ -1,7 +1,6 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{SBUS, MBUS}
import constellation.channel._
@@ -267,3 +266,26 @@ class SbusMeshNoCConfig extends Config(
new chipyard.config.AbstractConfig
)
class QuadRocketSbusRingNoCConfig extends Config(
new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0 " -> 0,
"Core 1 " -> 1,
"Core 2 " -> 2,
"Core 3 " -> 3,
"serial_tl" -> 4),
outNodeMapping = ListMap(
"system[0]" -> 5,
"system[1]" -> 6,
"system[2]" -> 7,
"system[3]" -> 8,
"pbus" -> 4)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
nocParams = NoCParams(
topology = UnidirectionalTorus1D(9),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
)) ++
new freechips.rocketchip.subsystem.WithNBigCores(4) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.AbstractConfig)

2
generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
View File

@@ -13,9 +13,9 @@ class NoCoresConfig extends Config(
new chipyard.config.WithNoUART ++
new chipyard.config.WithNoTileClockGaters ++
new chipyard.config.WithNoTileResetSetters ++
new chipyard.config.WithNoBusErrorDevices ++
new chipyard.config.WithNoDebug ++
new chipyard.config.WithNoPLIC ++
new chipyard.config.WithNoBusErrorDevices ++
new chipyard.config.AbstractConfig)
// A config that uses a empty chiptop module with no rocket-chip soc components

1
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -1,7 +1,6 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{MBUS}
// ---------------------------------------------------------

20
generators/chipyard/src/main/scala/config/RadianceConfigs.scala
View File

@@ -3,7 +3,8 @@ package chipyard
import chipyard.config.AbstractConfig
import chipyard.stage.phases.TargetDirKey
import freechips.rocketchip.devices.tilelink.BootROMLocated
import freechips.rocketchip.diplomacy.{AsynchronousCrossing, BigIntHexContext}
import freechips.rocketchip.prci.AsynchronousCrossing
import freechips.rocketchip.resources.BigIntHexContext
import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.Config
import radiance.memory._
@@ -52,16 +53,29 @@ class RadianceClusterConfig extends Config(
// new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++
// new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++
//
// note to hansung: somehow I don't have serializeUnaligned in my radiance subsystem files. I'll
// re-implement this with all the options instead of just this one
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
new radiance.subsystem.WithRadianceCluster(0) ++
new RadianceBaseConfig)
class RadianceClusterSmallConfig extends Config(
// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: true
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
new radiance.subsystem.WithRadianceCluster(0) ++
new RadianceBaseConfig)
class RadianceClusterSmem16KConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++
new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: false
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
new radiance.subsystem.WithRadianceCluster(0) ++

25
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
View File

@@ -1,7 +1,6 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------
// Configs with RoCC Accelerators
@@ -48,3 +47,27 @@ class AES256ECBRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(256) ++
new chipyard.config.AbstractConfig)
class ReRoCCTestConfig extends Config(
new rerocc.WithReRoCC ++
new chipyard.config.WithCharacterCountRoCC ++ // rerocc tile4 is charcnt
new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile3 is accum
new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile2 is accum
new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile1 is accum
new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile0 is accum
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class ReRoCCManyGemminiConfig extends Config(
new rerocc.WithReRoCC ++
new gemmini.LeanGemminiConfig ++ // rerocc tile3 is gemmini
new gemmini.LeanGemminiConfig ++ // rerocc tile2 is gemmini
new gemmini.LeanGemminiConfig ++ // rerocc tile1 is gemmini
new gemmini.LeanGemminiConfig ++ // rerocc tile0 is gemmini
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // 4 rocket cores
new chipyard.config.AbstractConfig)
class ZstdCompressorRocketConfig extends Config(
new compressacc.WithZstdCompressor ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

6
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -1,7 +1,7 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{InCluster}
// --------------
@@ -12,6 +12,10 @@ class RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig)
class DualRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig)
class TinyRocketConfig extends Config(
new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports
new testchipip.soc.WithNoScratchpads ++ // All memory is the Rocket TCMs

2
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -7,7 +7,7 @@ import chisel3.util.{log2Up}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import chipyard.stage.phases.TargetDirKey
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{XLen}

14
generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
View File

@@ -43,3 +43,17 @@ class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data](
}))
}
})
class WithAccumulatorRoCC(op: OpcodeSet = OpcodeSet.custom1) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => {
val accumulator = LazyModule(new AccumulatorExample(op, n = 4)(p))
accumulator
})
})
class WithCharacterCountRoCC(op: OpcodeSet = OpcodeSet.custom2) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => {
val counter = LazyModule(new CharacterCountExample(op)(p))
counter
})
})

2
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
View File

@@ -2,7 +2,7 @@ package chipyard.config
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{DTSTimebase}
import freechips.rocketchip.resources.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
// Replaces the L2 with a broadcast manager for maintaining coherence

2
generators/chipyard/src/main/scala/example/TutorialTile.scala
View File

@@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.prci._
// Example parameter class copied from CVA6, not included in documentation but for compile check only
// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure

9
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View File

@@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, HasCeaseIO, ChipyardSystem, ChipyardSystemModule}
import chipyard.example.{CanHavePeripheryGCD}
import scala.reflect.{ClassTag}
@@ -548,3 +549,11 @@ class WithNMITiedOff extends ComposeIOBinder({
(Nil, Nil)
}
})
class WithGCDBusyPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
val io_gcd_busy = IO(Output(Bool()))
io_gcd_busy := busy
(Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
}.getOrElse((Nil, Nil))
})

2
generators/chipyard/src/main/scala/iobinders/Ports.scala
View File

@@ -109,3 +109,5 @@ case class JTAGResetPort (val getIO: () => Reset)
case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle])
extends Port[HeterogeneousBag[TLBundle]]
case class GCDBusyPort (val getIO: () => Bool)
extends Port[Bool]

1
generators/compress-acc Submodule

Submodule generators/compress-acc added at 580fc99a8d

2
generators/constellation

Submodule generators/constellation updated: 6664839b10...5c9d27359d

2
generators/cva6

Submodule generators/cva6 updated: 9d1c106834...de4772f1d6

2
generators/diplomacy

Submodule generators/diplomacy updated: 055be698f4...6b7dc988a7

9
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -13,7 +13,8 @@ import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
import testchipip.cosim.{TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -370,6 +371,12 @@ class FireSimRadianceClusterSynConfig extends Config(
new WithFireSimConfigTweaks ++
new chipyard.RadianceClusterSynConfig)
class FireSimQuadRocketSbusRingNoCConfig extends Config(
new chipyard.config.WithNoTraceIO ++
new WithDefaultFireSimBridges ++
new WithFireSimConfigTweaks++
new chipyard.QuadRocketSbusRingNoCConfig)
class FireSimLargeBoomSV39CospikeConfig extends Config(
new firesim.firesim.WithCospikeBridge ++
new WithDefaultFireSimBridges ++

2
generators/hardfloat

Submodule generators/hardfloat updated: d93aa57080...4225367ed2

2
generators/ibex

Submodule generators/ibex updated: 89c19c2d7b...8a43aa70da

2
generators/icenet

Submodule generators/icenet updated: 969bc8f9a0...6fd35bf5a2

2
generators/radiance

Submodule generators/radiance updated: 5b4d34864f...37fd0c6200

1
generators/rerocc Submodule

Submodule generators/rerocc added at a22dce622d

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: ca0431493e...732cbe1990

2
generators/rocket-chip

Submodule generators/rocket-chip updated: c6fa6b918d...cd35968aa4

2
generators/rocket-chip-blocks

Submodule generators/rocket-chip-blocks updated: 2fc961f356...c8c14f7b47

2
generators/rocket-chip-inclusive-cache

Submodule generators/rocket-chip-inclusive-cache updated: 45d184f2fd...4aab5460bd

2
generators/rocket-gpu

Submodule generators/rocket-gpu updated: 080bfd706b...01eb6f1559

2
generators/shuttle

Submodule generators/shuttle updated: b75fada257...799263c618

2
generators/testchipip

Submodule generators/testchipip updated: 731d51ee15...9d8e830be4

21
scripts/generate-ckpt.sh
View File

@@ -13,6 +13,8 @@ usage() {
echo " -i <insns> : Instructions after PC to take checkpoint at [default 0]"
echo " -m <isa> : ISA to pass to spike for checkpoint generation [default rv64gc]"
echo " -o <out> : Output directory to store the checkpoint in. [default <elf>.<pc>.<insns>.loadarch]"
echo " -r <mem> : Memory regions to pass to spike. Passed to spike's '-m' flag. [default starting at 0x80000000 with 256MiB]"
echo " -v : Verbose"
exit "$1"
}
@@ -22,6 +24,8 @@ PC="0x80000000"
INSNS=0
ISA="rv64gc"
OUTPATH=""
MEMOVERRIDE=""
VERBOSE=0
while [ "$1" != "" ];
do
case $1 in
@@ -45,6 +49,11 @@ do
-o )
shift
OUTPATH=$1 ;;
-r )
shift
MEMOVERRIDE=$1 ;;
-v )
VERBOSE=1 ;;
* )
error "Invalid option $1"
usage 1 ;;
@@ -52,7 +61,15 @@ do
shift
done
BASEMEM="$((0x80000000)):$((0x10000000))"
if [[ $VERBOSE -eq 1 ]] ; then
set -x
fi
if [ -z "$MEMOVERRIDE" ] ; then
BASEMEM="$((0x80000000)):$((0x10000000))"
else
BASEMEM=$MEMOVERRIDE
fi
SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM"
BASENAME=$(basename -- $BINARY)
@@ -138,3 +155,5 @@ rm -rf mem.0x80000000.bin
riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF
rm -rf $RAWMEM_ELF
echo "Ensure that at minimum you have memory regions corresponding to $BASEMEM in downstream RTL tooling"

4
scripts/init-submodules-no-riscv-tools-nolog.sh
View File

@@ -74,6 +74,7 @@ cd "$RDIR"
toolchains/libgloss \
generators/gemmini \
generators/rocket-chip \
generators/compress-acc \
sims/firesim \
software/nvdla-workload \
software/coremark \
@@ -121,6 +122,9 @@ cd "$RDIR"
# Non-recursive clone
git submodule update --init generators/rocket-chip
# Non-recursive clone
git submodule update --init generators/compress-acc
# Minimal non-recursive clone to initialize sbt dependencies
git submodule update --init sims/firesim
git config --local submodule.sims/firesim.update none

184
scripts/insert-includes.py
View File

@@ -1,80 +1,134 @@
#!/usr/bin/env python
"""
replaces a `include with the full include file.
# replaces a `include with the full include file.
# recursively replaces `include's until none are left
#
# args
# $1 - file to remove includes from
# $2 - file to write output to
# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs)
# includes are found relative to this path
# this is equivalent to something like +incdir+
args
$1 - file which has includes to be replaced
$2 - file in which output will be written
$3 - list of directories to search for includes
(note: NON-RECURSIVE must specify all dirs)
includes are found relative to this path
this is equivalent to something like +incdir+
"""
import sys
import re
import os
import tempfile
import re
import shutil
import sys
import tempfile
inVlog = sys.argv[1]
outVlog = sys.argv[2]
print("[INFO] Replaces includes from: " + str(inVlog))
if inVlog == outVlog:
sys.exit("[ERROR] The input and output file cannot be the same.")
def print_info(msg):
"""
Print an info message.
# add directories to search list
incDirs = sys.argv[3:]
print("[INFO] Searching following dirs for includes: " + str(incDirs))
Args:
msg (str): message to print
"""
print(f"[INFO] {msg}")
def process(inF, outF):
# open file
with open(inF, 'r') as inFile:
with open(outF, 'w') as outFile:
# for each include found, search through all dirs and replace if found, error if not
for num, line in enumerate(inFile, 1):
match = re.match(r"^ *`include +\"(.*)\"", line)
if match and match.group(1) != "uvm_macros.svh":
print("[INFO] Replacing includes for {}".format(match.group(1)))
# search for include and replace
found = False
for d in incDirs:
potentialIncFileName = d + "/" + match.group(1)
if os.path.exists(potentialIncFileName):
found = True
print("[INFO] Found missing include in {}".format(potentialIncFileName))
with open(potentialIncFileName, 'r') as incFile:
for iline in incFile:
outFile.write(iline)
break
# must find something to include with
if not found:
sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
else:
outFile.write(line)
def print_error(msg, critical=True):
"""
Print an error message.
inF = inVlog
Args:
msg (str): message to print
critical (bool): whether to exit after printing the message
"""
if critical:
sys.exit(f"[ERROR] {msg}")
else:
print(f"[ERROR] {msg}")
while True:
# create a copy of the input
fd, temp_path = tempfile.mkstemp()
shutil.copy2(inF, temp_path)
with open(temp_path, 'r') as inFile:
anyIncludes = False
for line in inFile:
match = re.match(r"^ *`include +\"(.*)\"", line)
if match:
anyIncludes = True
break
def find_include(file_name, inc_dirs):
"""
Find the include file in the list of directories.
if anyIncludes:
process(temp_path, outVlog)
inF = outVlog
os.remove(temp_path)
else:
os.remove(temp_path)
break
Args:
file_name (str): include file name
inc_dirs (list): list of directories to search for includes
print("[INFO] Success. Writing output to: " + str(outVlog))
Returns:
str: full path to the include file
"""
for d in inc_dirs:
inc_file_name = d + "/" + file_name
if os.path.exists(inc_file_name):
return inc_file_name
print_error(f"Include file {file_name} not found in {inc_dirs}")
return None
def process_helper(in_fname, out_f, inc_dirs, replaced_includes):
"""
Helper function to DFS through include files and replace includes.
"""
include_regex = re.compile(r"^ *`include +\"(.*)\"")
# slurp the input file.
# this avoids having a bunch of fds open during recursion
with open(in_fname, "r", encoding="utf-8") as in_file:
lines = in_file.readlines()
for num, line in enumerate(lines, 1):
match = re.match(include_regex, line)
if not match or match.group(1) == "uvm_macros.svh":
# copy the line as is
out_f.write(line)
continue
if match.group(1) in replaced_includes:
print_info("Skipping duplicate include")
continue
print_info(
f"Replacing includes for {match.group(1)}" f" at line {num}"
)
# search for include and replace
inc_file_name = find_include(match.group(1), inc_dirs)
replaced_includes.add(match.group(1))
process_helper(inc_file_name, out_f, inc_dirs, replaced_includes)
def process(in_fname, out_fname, inc_dirs=None):
"""
Replace include directives in a file with the full include file.
Args:
in_fname (str): input file name
out_fname (str): output file name
inc_dirs (list): list of directories to search for includes
"""
replaced_includes = set()
with open(out_fname, "w", encoding="utf-8") as out_file:
process_helper(in_fname, out_file, inc_dirs, replaced_includes)
def main():
"""
Entry point for the script.
Args:
<input file> <output file> <list of directories to search for includes>
"""
in_vlog = sys.argv[1]
out_vlog = sys.argv[2]
if in_vlog == out_vlog:
sys.exit("[ERROR] The input and output file cannot be the same.")
# add directories to search list
inc_dirs = sys.argv[3:]
print("[INFO] Replaces includes from: " + str(in_vlog))
print("[INFO] Searching following dirs for includes: " + str(inc_dirs))
# make a copy of the input file
_, temp_path = tempfile.mkstemp()
shutil.copy2(in_vlog, temp_path)
process(temp_path, out_vlog, inc_dirs)
print("[INFO] Success. Output written to: " + str(out_vlog))
if __name__ == "__main__":
main()

8
scripts/uniquify-module-names.py
View File

@@ -11,6 +11,7 @@ parser = argparse.ArgumentParser(description="")
parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.")
parser.add_argument("--top-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.")
parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).')
parser.add_argument('--in-bb-filelist', type=str, required=True, help='Path to input blackbox filelist')
parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.")
parser.add_argument("--model", type=str, required=True, help="Name of the Model module.")
parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.')
@@ -57,8 +58,8 @@ def get_modules_in_verilog_file(file):
module_names.append(words[1].replace("(", "").replace(")", "").replace(";", ""))
return module_names
def get_modules_in_filelist(verilog_module_filename, cc_filelist):
with open(args.in_all_filelist) as fl:
def get_modules_in_filelist(filelist, verilog_module_filename, cc_filelist):
with open(filelist) as fl:
lines = fl.readlines()
for line in lines:
path = line.strip()
@@ -186,7 +187,8 @@ def uniquify_modules_under_model(modules_under_model, common_modules, verilog_mo
def main():
verilog_module_filename = dict()
cc_filelist = list()
get_modules_in_filelist(verilog_module_filename, cc_filelist)
get_modules_in_filelist(args.in_all_filelist, verilog_module_filename, cc_filelist)
get_modules_in_filelist(args.in_bb_filelist , verilog_module_filename, cc_filelist)
modules_under_model = get_modules_under_hier(args.model_hier_json, args.dut)
modules_under_top = get_modules_under_hier(args.top_hier_json)

2
software/firemarshal

Submodule software/firemarshal updated: b014183ac6...0c0cdfeb26

2
toolchains/riscv-tools/riscv-pk

Submodule toolchains/riscv-tools/riscv-pk updated: e8e6b3aaee...4f3debe4d0

2
tools/circt

Submodule tools/circt updated: 9e0c1696f3...481cb60add

2
tools/rocket-dsp-utils

Submodule tools/rocket-dsp-utils updated: c4c638da02...6ee2309f80

12
variables.mk
View File

@@ -157,16 +157,16 @@ long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
# classpaths
CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache
CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar
# The generator classpath must contain the Generator main
GENERATOR_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar
# The tapeout classpath must contain MacroCompiler
TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar
# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))
# chisel generated outputs
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
CHISEL_LOG_FILE ?= $(build_dir)/$(long_name).chisel.log
FIRTOOL_LOG_FILE ?= $(build_dir)/$(long_name).firtool.log
# chisel anno modification output
MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json
@@ -210,10 +210,6 @@ EXT_INCDIRS ?=
BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img bootrom.radiance.rv32.img
BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
# custom *.bin argument files needed for Radiance
ARGSROM_FILES ?= args.bin op_a.bin op_b.bin
ARGSROM_TARGETS ?= $(addprefix $(base_dir)/sims/, $(ARGSROM_FILES))
# files that contain lists of files needed for VCS or Verilator simulation
SIM_FILE_REQS =
sim_files ?= $(build_dir)/sim_files.f

2
vlsi/example-designs/sky130-commercial.yml
View File

@@ -2,7 +2,7 @@
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"}
{name: "clock_uncore", period: "30ns", uncertainty: "2ns"}
]
# Placement Constraints

5
vlsi/example-designs/sky130-openroad-rockettile.yml
View File

@@ -1,7 +1,7 @@
# Override configurations in ../example-sky130.yml and example-designs
# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore"
vlsi.inputs.clocks: [
{name: "clock", period: "30ns", uncertainty: "3ns"}
]
@@ -22,7 +22,7 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
# data cache
# data cache
- path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
@@ -47,3 +47,4 @@ vlsi.inputs.placement_constraints:
x: 50
y: 2100
orientation: r90

23
vlsi/example-designs/sky130-openroad.yml
View File

@@ -3,7 +3,7 @@
# Specify clock signals
# Relax the clock period for OpenROAD to meet timing
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
{name: "clock_uncore", period: "50ns", uncertainty: "2ns"}
]
# Flow parameters that yield a routable design with reasonable timing
@@ -54,36 +54,27 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
# data cache
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 450
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 850
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1250
y: 800
orientation: r90
# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1600
orientation: r90
# instruction cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100

2
vlsi/example-designs/sky130-rocket.yml
View File

@@ -1,7 +1,7 @@
# Override configurations in ../example-sky130.yml and example-designs
# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore"
vlsi.inputs.clocks: [
{name: "clock", period: "5ns", uncertainty: "1ns"}
]

12
vlsi/example-sky130.yml
View File

@@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
{name: "clock_uncore", period: "20ns", uncertainty: "1ns"}
]
# Generate Make include to aid in flow
@@ -42,27 +42,27 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
# data cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
# data cache
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 800
orientation: r90
# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1600
orientation: r90
# instruction cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100