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Punch out reset in AXI4MMIO IOBinder

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This commit is contained in:
David Biancolin
2020-10-15 10:00:07 -07:00
parent 9c8d2948af
commit 74c1c9d7ab
1 changed files with 5 additions and 3 deletions
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8
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -282,10 +282,12 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({
class WithAXI4MMIOPunchthrough extends OverrideIOBinder({ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({
(system: CanHaveMasterAXI4MMIOPort) => { (system: CanHaveMasterAXI4MMIOPort) => {
val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
p.bits <> m p.bits <> m
p.clock := BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock) val mbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS)
p.clock := BoreHelper("axi4_mmio_clock", mbus.module.clock)
p.reset := BoreHelper("axi4_mmio_reset", mbus.module.reset)
p p
}) })
(ports, Nil) (ports, Nil)