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Merge remote-tracking branch 'origin/graphics' into graphics

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This commit is contained in:
Hansung Kim
2024-04-29 15:05:27 -07:00
parent 89deaf4bd2 5a98716a1e
commit 74c9eef997
98 changed files with 2164 additions and 1568 deletions
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2
.github/scripts/check-commit.sh vendored
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@@ -45,7 +45,7 @@ search () {
done
}
submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
dir="generators"
branches=("master" "main" "dev")
search

18
.github/scripts/defaults.sh vendored
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@@ -28,12 +28,12 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric"
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-gpu"]="chipyard-radiance chipyard-radiance-fuzzer chipyard-coalescer coalescer"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
@@ -48,8 +48,10 @@ mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog"
mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig"
mapping["chipyard-boomv3"]=" CONFIG=MediumBoomV3CosimConfig"
mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
@@ -60,10 +62,12 @@ mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_S
mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomV3Config verilog"
mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
mapping["tracegen-boomv3"]=" CONFIG=BoomV3TraceGenConfig"
mapping["tracegen-boomv4"]=" CONFIG=BoomV4TraceGenConfig"
mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"

21
.github/scripts/run-tests.sh vendored
View File

@@ -46,13 +46,21 @@ case $1 in
$LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
;;
chipyard-boom)
chipyard-boomv3)
run_bmark
;;
chipyard-boomv4)
run_bmark
;;
chipyard-shuttle)
run_bmark ${mapping[$1]}
;;
chipyard-dmiboom)
chipyard-dmiboomv3)
# Test checkpoint-restore
$LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
;;
chipyard-dmiboomv4)
# Test checkpoint-restore
$LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
@@ -122,10 +130,17 @@ case $1 in
make -C $LOCAL_CHIPYARD_DIR/tests
run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
;;
chipyard-llcchiplet)
make -C $LOCAL_CHIPYARD_DIR/tests
run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
;;
tracegen)
run_tracegen
;;
tracegen-boom)
tracegen-boomv3)
run_tracegen
;;
tracegen-boomv4)
run_tracegen
;;
chipyard-cva6)

120
.github/workflows/chipyard-run-tests.yml vendored
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@@ -455,8 +455,8 @@ jobs:
group-key: "group-cores"
project-key: "chipyard-hetero"
chipyard-boom-run-tests:
name: chipyard-boom-run-tests
chipyard-boomv3-run-tests:
name: chipyard-boomv3-run-tests
needs: prepare-chipyard-cores
runs-on: as4
steps:
@@ -476,7 +476,30 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-boom"
project-key: "chipyard-boomv3"
chipyard-boomv4-run-tests:
name: chipyard-boomv4-run-tests
needs: prepare-chipyard-cores
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v4
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-boomv4"
chipyard-shuttle-run-tests:
name: chipyard-shuttle-run-tests
@@ -616,8 +639,8 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-dmirocket"
chipyard-dmiboom-run-tests:
name: chipyard-dmiboom-run-tests
chipyard-dmiboomv3-run-tests:
name: chipyard-dmiboomv3-run-tests
needs: prepare-chipyard-peripherals
runs-on: as4
steps:
@@ -637,7 +660,30 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-dmiboom"
project-key: "chipyard-dmiboomv3"
chipyard-dmiboomv4-run-tests:
name: chipyard-dmiboomv4-run-tests
needs: prepare-chipyard-peripherals
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v4
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-dmiboomv4"
chipyard-spiflashwrite-run-tests:
name: chipyard-spiflashwrite-run-tests
@@ -731,6 +777,29 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-symmetric"
chipyard-llcchiplet-run-tests:
name: chipyard-llcchiplet-run-tests
needs: prepare-chipyard-peripherals
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-llcchiplet"
chipyard-sha3-run-tests:
name: chipyard-sha3-run-tests
needs: prepare-chipyard-accels
@@ -847,8 +916,8 @@ jobs:
project-key: "chipyard-mempress"
tracegen-boom-run-tests:
name: tracegen-boom-run-tests
tracegen-boomv3-run-tests:
name: tracegen-boomv3-run-tests
needs: prepare-chipyard-tracegen
runs-on: as4
steps:
@@ -868,7 +937,30 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-tracegen"
project-key: "tracegen-boom"
project-key: "tracegen-boomv3"
tracegen-boomv4-run-tests:
name: tracegen-boomv4-run-tests
needs: prepare-chipyard-tracegen
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v4
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-tracegen"
project-key: "tracegen-boomv4"
tracegen-run-tests:
name: tracegen-run-tests
@@ -1084,24 +1176,28 @@ jobs:
documentation-check,
chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
chipyard-boom-run-tests,
chipyard-boomv3-run-tests,
chipyard-boomv4-run-tests,
chipyard-shuttle-run-tests,
chipyard-cva6-run-tests,
chipyard-ibex-run-tests,
chipyard-sodor-run-tests,
chipyard-dmiboom-run-tests,
chipyard-dmiboomv3-run-tests,
chipyard-dmiboomv4-run-tests,
chipyard-dmirocket-run-tests,
chipyard-spiflashwrite-run-tests,
chipyard-manyperipherals-run-tests,
chipyard-tethered-run-tests,
chipyard-symmetric-run-tests,
chipyard-llcchiplet-run-tests,
chipyard-sha3-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
chipyard-prefetchers-run-tests,
chipyard-mempress-run-tests,
chipyard-constellation-run-tests,
tracegen-boom-run-tests,
tracegen-boomv3-run-tests,
tracegen-boomv4-run-tests,
tracegen-run-tests,
icenet-run-tests,
testchipip-run-tests,

2
.github/workflows/update-circt.yml vendored
View File

@@ -16,7 +16,7 @@ jobs:
runs-on: ubuntu-latest
steps:
- name: Update CIRCT
uses: circt/update-circt@v1.0.0
uses: circt/update-circt@v1
with:
user: 'bartender'
email: 'firesimchipyard@gmail.com'

6
.gitmodules vendored
View File

@@ -22,6 +22,9 @@
[submodule "generators/icenet"]
path = generators/icenet
url = https://github.com/firesim/icenet.git
[submodule "tools/circt"]
path = tools/circt
url = https://github.com/llvm/circt.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
@@ -49,6 +52,9 @@
[submodule "generators/cva6"]
path = generators/cva6
url = https://github.com/ucb-bar/cva6-wrapper.git
[submodule "generators/diplomacy"]
path = generators/diplomacy
url = https://github.com/chipsalliance/diplomacy.git
[submodule "tools/DRAMSim2"]
path = tools/DRAMSim2
url = https://github.com/firesim/DRAMSim2.git

16
build.sbt
View File

@@ -113,8 +113,19 @@ lazy val rocketMacros = (project in rocketChipDir / "macros")
)
)
lazy val diplomacy = freshProject("diplomacy", file("generators/diplomacy/diplomacy"))
.dependsOn(cde)
.settings(commonSettings)
.settings(chiselSettings)
.settings(Compile / scalaSource := baseDirectory.value / "diplomacy")
.settings(
libraryDependencies ++= Seq(
"com.lihaoyi" %% "sourcecode" % "0.3.1"
)
)
lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.dependsOn(hardfloat, rocketMacros, cde)
.dependsOn(hardfloat, rocketMacros, diplomacy, cde)
.settings(commonSettings)
.settings(chiselSettings)
.settings(
@@ -123,7 +134,8 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "4.0.5",
"org.scalatest" %% "scalatest" % "3.2.0" % "test",
"org.scala-graph" %% "graph-core" % "1.13.5"
"org.scala-graph" %% "graph-core" % "1.13.5",
"com.lihaoyi" %% "sourcecode" % "0.3.1"
)
)
.settings( // Settings for scalafix

38
common.mk
View File

@@ -195,7 +195,7 @@ SFC_MFC_TARGETS = \
$(GEN_COLLATERAL_DIR)
SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
# DOC include start: FirrtlCompiler
# There are two possible cases for this step. In the first case, SFC
@@ -312,8 +312,13 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_S
# note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated,
# however it is really unneeded since ALL_MODS_FILELIST includes all BB files
########################################################################################
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST)
sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) $(EXT_FILELISTS)
ifneq (,$(EXT_FILELISTS))
cat $(EXT_FILELISTS) > $@
else
rm -f $@
endif
sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' >> $@
echo "$(TOP_SMEMS_FILE)" >> $@
echo "$(MODEL_SMEMS_FILE)" >> $@
@@ -373,14 +378,27 @@ run-binary: check-binary $(BINARY).run
run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
%.run: %.check-exists $(SIM_PREREQ) | $(output_dir)
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
(set -o pipefail && $(NUMA_PREFIX) $(sim) \
$(PERMISSIVE_ON) \
$(call get_common_sim_flags,$*) \
$(VERBOSE_FLAGS) \
$(PERMISSIVE_OFF) \
$* \
$(BINARY_ARGS) \
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
# run simulator as fast as possible (no insn disassembly)
run-binary-fast: check-binary $(BINARY).run.fast
run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
%.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir)
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* </dev/null | tee $(call get_sim_out_name,$*).log)
(set -o pipefail && $(NUMA_PREFIX) $(sim) \
$(PERMISSIVE_ON) \
$(call get_common_sim_flags,$*) \
$(PERMISSIVE_OFF) \
$* \
$(BINARY_ARGS) \
</dev/null | tee $(call get_sim_out_name,$*).log)
# run simulator with as much debug info as possible
run-binary-debug: check-binary $(BINARY).run.debug
@@ -388,7 +406,15 @@ run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))
%.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \
$(PERMISSIVE_ON) \
$(call get_common_sim_flags,$*) \
$(VERBOSE_FLAGS) \
$(call get_waveform_flag,$(call get_sim_out_name,$*)) \
$(PERMISSIVE_OFF) \
$* \
$(BINARY_ARGS) \
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
run-fast: run-asm-tests-fast run-bmark-tests-fast

6
conda-reqs/chipyard-base.yaml
View File

@@ -14,8 +14,8 @@ dependencies:
# instructions on adding a recipe
# https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
# documentation on package_spec syntax for constraining versions
- gcc<12
- gxx<12
- gcc=13.2
- gxx=13.2
- sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
- conda-gcc-specs
- binutils
@@ -31,5 +31,5 @@ dependencies:
- sbt
- openjdk=20
- dtc
- verilator==5.020
- verilator==5.022
- conda-lock=1.4

2
conda-reqs/circt.json
View File

@@ -1,3 +1,3 @@
{
"version": "firtool-1.61.0"
"version": "firtool-1.66.0"
}

368
conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
View File

@@ -9,7 +9,7 @@
# To update a single package to the latest version compatible with the version constraints in the source:
# conda-lock lock --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml --update PACKAGE
# To re-solve the entire environment, e.g. after changing a version constraint in the source file:
# conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
# conda-lock -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
metadata:
channels:
- url: ucb-bar
@@ -21,13 +21,13 @@ metadata:
- url: nodefaults
used_env_vars: []
content_hash:
linux-64: b3d6181ced7140e828bceb01703958b116fa5c544d3f5a8ce512f808f5ed3c35
linux-64: 82a67811dd17c821d0f6126f25e6fc23833d67f6b990ee3139ff0bea2b0ddf59
platforms:
- linux-64
sources:
- /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml
- /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml
- /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml
- /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml
- /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml
- /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/esp-tools.yaml
package:
- category: main
dependencies: {}
@@ -43,13 +43,13 @@ package:
- category: main
dependencies: {}
hash:
md5: f6ce7955b53ae1ca83144adb3be9c600
sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2
md5: 38d211c448a67f12fe693fe25df4da23
sha256: 0dbeaddc3d5134b5336c52ac05642533b8d1ba2e1316aa92981f4cf5b5388de0
manager: conda
name: _sysroot_linux-64_curr_repodata_hack
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda
url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_14.conda
version: '3'
- category: main
dependencies: {}
@@ -120,25 +120,25 @@ package:
- category: main
dependencies: {}
hash:
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dependencies:
python: ''
@@ -1785,14 +1782,14 @@ package:
dependencies:
python: '>=3.7'
hash:
md5: 074d0ce7a6261ab8b497c3518796ef3e
sha256: 53cc436ab92d38683df1320e4468a8b978428e800195bf1c8c2460e90b0bc117
md5: 37c47ea93ef00dd80d880fc4ba21256a
sha256: 8d45c266bf919788abacd9828f4a2101d7216f6d4fc7c8d3417034fe0d795a18
manager: conda
name: tomlkit
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.12.3-pyha770c72_0.conda
version: 0.12.3
url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.12.4-pyha770c72_0.conda
version: 0.12.4
- category: main
dependencies:
python: '>=3.7'
@@ -1811,26 +1808,26 @@ package:
python: '>=3.9,<3.10.0a0'
python_abi: 3.9.* *_cp39
hash:
md5: cbe186eefb0bcd91e8f47c3908489874
sha256: dc0df742be0e83a4286137d21f60ca829632c2ffd66d3bebb603afe5ce74cc68
md5: 1e865e9188204cdfb1fd2531780add88
sha256: 27ab8f208c9a8fef7341d8f603059073f445de39c52eed73218f5823212ca73c
manager: conda
name: tornado
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.3.3-py39hd1e30aa_1.conda
version: 6.3.3
url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.4-py39hd1e30aa_0.conda
version: '6.4'
- category: main
dependencies:
python: '>=3.8'
hash:
md5: a92a6440c3fe7052d63244f3aba2a4a7
sha256: f3c5be8673bfd905c4665efcb27fa50192f24f84fa8eff2f19cba5d09753d905
md5: 16ae769069b380646c47142d719ef466
sha256: 4be24d557897b2f6609f5d5f7c437833c62f4d4a96581e39530067e96a2d0451
manager: conda
name: typing_extensions
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.9.0-pyha770c72_0.conda
version: 4.9.0
url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.10.0-pyha770c72_0.conda
version: 4.10.0
- category: main
dependencies:
flex: '>=2.6.4,<3.0a0'
@@ -1842,14 +1839,14 @@ package:
perl: ''
python: ''
hash:
md5: 0b2929f84fe7d3a6117439507d5d50d9
sha256: 1d6af07d2d19be7adc296e8b6c43bd3eb12b48d8ab8e0cec566e8f9872661813
md5: d628a7f32222786b70ad81e56dd4a61a
sha256: 1648f885c97e5189adb12a70eef72699885a4e9e882ea385c3cd904baed251ce
manager: conda
name: verilator
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.020-h7cd9344_0.conda
version: '5.020'
url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.022-h7cd9344_0.conda
version: '5.022'
- category: main
dependencies:
python: '>=2.6'
@@ -2067,27 +2064,27 @@ package:
python: '>=3.8'
zipp: '>=0.5'
hash:
md5: 746623a787e06191d80a2133e5daff17
sha256: e72d05f171f4567004c9360a838e9d5df21e23dcfeb945066b53a6e5f754b861
md5: b050a4bb0e90ebd6e7fa4093d6346867
sha256: 9a26136d2cc81ccac209d6ae24281ceba3365fe34e34b2c45570f2a96e9d9c1b
manager: conda
name: importlib-metadata
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-7.0.1-pyha770c72_0.conda
version: 7.0.1
url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-7.0.2-pyha770c72_0.conda
version: 7.0.2
- category: main
dependencies:
more-itertools: ''
python: '>=3.7'
hash:
md5: e9f79248d30e942f7c358ff21a1790f5
sha256: 14f5240c3834e1b784dd41a5a14392d9150dff62a74ae851f73e65d2e2bbd891
md5: c541ae264c9f1f21d83fc30dffb908ee
sha256: 232b40de8176fa7fb66a893653f8ae03c29616e04a83dae5a47df94b74e256ca
manager: conda
name: jaraco.classes
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/jaraco.classes-3.3.0-pyhd8ed1ab_0.conda
version: 3.3.0
url: https://conda.anaconda.org/conda-forge/noarch/jaraco.classes-3.3.1-pyhd8ed1ab_0.conda
version: 3.3.1
- category: main
dependencies:
markupsafe: '>=2.0'
@@ -2136,28 +2133,27 @@ package:
python: '>=3.9,<3.10.0a0'
python_abi: 3.9.* *_cp39
ruamel.yaml.clib: '>=0.1.2'
setuptools: ''
hash:
md5: 2b447c949fba3e4c95e7f7dae77f5ebd
sha256: 78638b0ef756443722f91a3bc0225b1ac79757be3d1f313a754c49cd3a3e2227
md5: 2289054e90cf07e35280bbe798811dc8
sha256: 9cfb534d18a1c060d876762806752d6a3d253727f255c65e5473810dd1dd4231
manager: conda
name: ruamel.yaml
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.5-py39hd1e30aa_0.conda
version: 0.18.5
url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.6-py39hd1e30aa_0.conda
version: 0.18.6
- category: main
dependencies:
typing_extensions: 4.9.0 pyha770c72_0
typing_extensions: 4.10.0 pyha770c72_0
hash:
md5: c16524c1b7227dc80b36b4fa6f77cc86
sha256: d795c1eb1db4ea147f01ece74e5a504d7c2e8d5ee8c11ec987884967dd938f9c
md5: 091683b9150d2ebaa62fd7e2c86433da
sha256: 0698fe2c4e555fb44c27c60f7a21fa0eea7f5bf8186ad109543c5b056e27f96a
manager: conda
name: typing-extensions
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.9.0-hd8ed1ab_0.conda
version: 4.9.0
url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.10.0-hd8ed1ab_0.conda
version: 4.10.0
- category: main
dependencies:
brotli-python: '>=1.0.9'
@@ -2179,14 +2175,14 @@ package:
platformdirs: <5,>=3.9.1
python: '>=3.8'
hash:
md5: c119653cba436d8183c27bf6d190e587
sha256: 50827c3721a9dbf973b568709d4381add2a6552fa562f26a385c5edc16a534af
md5: 8797a4e26be36880a603aba29c785352
sha256: 1ced4445cf72cd9dc344ad04bdaf703a08cc428c8c46e4bda928ad79786ee153
manager: conda
name: virtualenv
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.0-pyhd8ed1ab_0.conda
version: 20.25.0
url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.1-pyhd8ed1ab_0.conda
version: 20.25.1
- category: main
dependencies:
libgcc-ng: '>=9.3.0'
@@ -2220,18 +2216,18 @@ package:
dependencies:
cffi: '>=1.12'
libgcc-ng: '>=12'
openssl: '>=3.1.5,<4.0a0'
openssl: '>=3.2.1,<4.0a0'
python: '>=3.9,<3.10.0a0'
python_abi: 3.9.* *_cp39
hash:
md5: fee371764cdabeffc4f89a06688deb08
sha256: 56b8d01515d58bf5e368f01286485f9f3095bbede487ffa9f9367f6978eba07f
md5: 74adeac31d6368a9dcf1a867a052cffa
sha256: dbde9bd3cc0400cdefbdfe7a41ddb7cb33efc472dbd291485308eb5f5830f1a9
manager: conda
name: cryptography
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.2-py39he6105cc_0.conda
version: 42.0.2
url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.5-py39hd4f0224_0.conda
version: 42.0.5
- category: main
dependencies:
curl: ''
@@ -2240,18 +2236,18 @@ package:
libgcc-ng: '>=12'
libiconv: '>=1.17,<2.0a0'
libzlib: '>=1.2.13,<1.3.0a0'
openssl: '>=3.2.0,<4.0a0'
pcre2: '>=10.42,<10.43.0a0'
openssl: '>=3.2.1,<4.0a0'
pcre2: '>=10.43,<10.44.0a0'
perl: 5.*
hash:
md5: 851970792301b407ba4c35e75e796791
sha256: 73a065e160d759e8fb0b169e615955a8fe0c148ed00c7f6ddf076f2e4adfd765
md5: 6817894081347566c0f097216bb36faa
sha256: 3ca58462b1c79a288587f8bdb82aa55829586e3f1635650988ab95d845b1b68e
manager: conda
name: git
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/git-2.43.0-pl5321h7bc287a_0.conda
version: 2.43.0
url: https://conda.anaconda.org/conda-forge/linux-64/git-2.44.0-pl5321h709897a_0.conda
version: 2.44.0
- category: main
dependencies:
cairo: '>=1.18.0,<2.0a0'
@@ -2272,16 +2268,16 @@ package:
version: 8.3.0
- category: main
dependencies:
importlib-metadata: '>=7.0.1,<7.0.2.0a0'
importlib-metadata: '>=7.0.2,<7.0.3.0a0'
hash:
md5: 4a2f43a20fa404b998859c6a470ba316
sha256: bc362df1d4f5a04c38dff29cd9c2d0ac584f9c4b45d3e4683ee090944a38fba4
md5: d11132727a247f2c1998779a2af743a1
sha256: b250e6a3e741b762bb2caf05119feb6245cb41b468542e5a9263cd01671098f7
manager: conda
name: importlib_metadata
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.1-hd8ed1ab_0.conda
version: 7.0.1
url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.2-hd8ed1ab_0.conda
version: 7.0.2
- category: main
dependencies:
libgcc-ng: '>=12'
@@ -2289,14 +2285,14 @@ package:
python_abi: 3.9.* *_cp39
typing-extensions: '>=4.6.0,!=4.7.0'
hash:
md5: bf093850e0507bfaf8c1cabfd277d06b
sha256: 8896019379cab43cff61c8f16166db9f328317590fe61d897bb9ce8df2b7e900
md5: 35fef239167838ec05bc714a70fbd6d9
sha256: c0c9ebdcd812ac6c35e85a37bae966b461b5d390aeecf168611c4abd43c947a8
manager: conda
name: pydantic-core
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.2-py39h9fdd4d6_0.conda
version: 2.16.2
url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.3-py39h9fdd4d6_0.conda
version: 2.16.3
- category: main
dependencies:
certifi: '>=2017.4.17'
@@ -2363,7 +2359,7 @@ package:
version: 1.4.4
- category: main
dependencies:
alsa-lib: '>=1.2.10,<1.2.11.0a0'
alsa-lib: '>=1.2.10,<1.3.0.0a0'
fontconfig: '>=2.14.2,<3.0a0'
fonts-conda-ecosystem: ''
freetype: '>=2.12.1,<3.0a0'
@@ -2394,18 +2390,18 @@ package:
- category: main
dependencies:
annotated-types: '>=0.4.0'
pydantic-core: 2.16.2
pydantic-core: 2.16.3
python: '>=3.7'
typing-extensions: '>=4.6.1'
hash:
md5: 3b1698c91820d852d802fc21471f52d8
sha256: 27083637287bb08a93e28616b5030f5eab31deb83d16fc132901ada987a62cfa
md5: 4f4e78b41c489b89d98719fcbde09361
sha256: 7367461b8f9e309f20f129605daa78635a1daa2538fe0b40d7f7238f8d430a29
manager: conda
name: pydantic
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.1-pyhd8ed1ab_0.conda
version: 2.6.1
url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.3-pyhd8ed1ab_0.conda
version: 2.6.3
- category: main
dependencies:
cryptography: ''
@@ -2445,14 +2441,14 @@ package:
python_abi: 3.9.* *_cp39
secretstorage: '>=3.2'
hash:
md5: 1426c4f9994cb7e55859b44b98bc7b3e
sha256: a7538a914feb54dc3e7ee46431af5f0a40e668b29224998e6d3be044a1a7606e
md5: 2482396e5d629d60526bce6268cfde6a
sha256: 8d231971f2ab5a9ab17d0b792021e287b982cb28c5258a93076a7fb937fa40c5
manager: conda
name: keyring
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.0-py39hf3d152e_0.conda
version: 24.3.0
url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.1-py39hf3d152e_0.conda
version: 24.3.1
- category: main
dependencies:
__unix: ''

851
conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml generated
View File

File diff suppressed because it is too large Load Diff

388
conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
View File

@@ -9,7 +9,7 @@
# To update a single package to the latest version compatible with the version constraints in the source:
# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml --update PACKAGE
# To re-solve the entire environment, e.g. after changing a version constraint in the source file:
# conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
# conda-lock -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
metadata:
channels:
- url: ucb-bar
@@ -21,13 +21,13 @@ metadata:
- url: nodefaults
used_env_vars: []
content_hash:
linux-64: 992d6d7f85dd948e8f14b610157acfaad2453e8a2cd692e30ad1a3c340fdbd88
linux-64: b90f846250ea3712ec4443d75b88f209e3f4e6082da4c655963a79121db7ea28
platforms:
- linux-64
sources:
- /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml
- /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml
- /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml
- /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml
- /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml
- /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/riscv-tools.yaml
package:
- category: main
dependencies: {}
@@ -43,13 +43,13 @@ package:
- category: main
dependencies: {}
hash:
md5: f6ce7955b53ae1ca83144adb3be9c600
sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2
md5: 38d211c448a67f12fe693fe25df4da23
sha256: 0dbeaddc3d5134b5336c52ac05642533b8d1ba2e1316aa92981f4cf5b5388de0
manager: conda
name: _sysroot_linux-64_curr_repodata_hack
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda
url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_14.conda
version: '3'
- category: main
dependencies: {}
@@ -120,25 +120,25 @@ package:
- category: main
dependencies: {}
hash:
md5: fb94f6b17ef1a75faac2e06937dc4223
sha256: 86d1e11bf0b8dbc74fec07f3c71bb1b20f83e32b5b9f8625b3dc653ce00e40bd
md5: 3bc29a967fee57e193ce51f51c598bca
sha256: 858029ad4d66869c533bb5a22e95e7c044ca66c61d6f403f10d9ae074a0e360e
manager: conda
name: libgcc-devel_linux-64
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_105.conda
version: 11.4.0
url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-13.2.0-ha9c7c90_105.conda
version: 13.2.0
- category: main
dependencies: {}
hash:
md5: a884fe2f11c6167f3dc62d4b1db20ced
sha256: 20c4f2b96b8fb57a3cad0bb8f1ce407ee7bc935cb0ce68b430b10b77616c0b16
md5: 66383205c2e1bdf013df52fa9e3e6763
sha256: 67e999ee56481844ca4ce2e61132c5c16f3f00a05daa1d0ea4b2c684eea5de5a
manager: conda
name: libstdcxx-devel_linux-64
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_105.conda
version: 11.4.0
url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-13.2.0-ha9c7c90_105.conda
version: 13.2.0
- category: main
dependencies: {}
hash:
@@ -191,13 +191,13 @@ package:
dependencies:
_sysroot_linux-64_curr_repodata_hack: 3.*
hash:
md5: 523bc836a954faf0cca94831971bb85a
sha256: 67a3caa56e2a59f407f3d290437b865aaf996873006e2fcfca6295d0f0be8db9
md5: f6c14886b1695a2462d296176e831080
sha256: 604b9345a7a1474b7eb33260e382446754d16eed754b853d7571d0e39bfc7737
manager: conda
name: kernel-headers_linux-64
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_14.conda
version: 3.10.0
- category: main
dependencies:
@@ -239,15 +239,15 @@ package:
- category: main
dependencies:
_sysroot_linux-64_curr_repodata_hack: 3.*
kernel-headers_linux-64: 3.10.0 h4a8ded7_13
kernel-headers_linux-64: 3.10.0 h4a8ded7_14
hash:
md5: 57e5a5191ffe999b9f4dfdbcd0ddcba4
sha256: f09f2fea4b571dcd225f1e35bd3c851e809cd4c2f5f151438133969ab28478e5
md5: d5f7a1cca06f56e6ac2b525f199f9b9e
sha256: af0f9ed466f97e3910c1d867ab44c974e01383cb408baa38606265964c7f0857
manager: conda
name: sysroot_linux-64
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_13.tar.bz2
url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_14.conda
version: '2.17'
- category: main
dependencies:
@@ -279,14 +279,14 @@ package:
dependencies:
libgcc-ng: '>=12'
hash:
md5: 75dae9a4201732aa78a530b826ee5fe0
sha256: 51147922bad9d3176e780eb26f748f380cd3184896a9f9125d8ac64fe330158b
md5: 0bb492cca54017ea314b809b1ee3a176
sha256: 0e2b75b9834a6e520b13db516f7cf5c9cea8f0bbc9157c978444173dacb98fec
manager: conda
name: alsa-lib
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.10-hd590300_0.conda
version: 1.2.10
url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.11-hd590300_1.conda
version: 1.2.11
- category: main
dependencies:
binutils_impl_linux-64: '>=2.40,<2.41.0a0'
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sha256: 1d6af07d2d19be7adc296e8b6c43bd3eb12b48d8ab8e0cec566e8f9872661813
md5: d628a7f32222786b70ad81e56dd4a61a
sha256: 1648f885c97e5189adb12a70eef72699885a4e9e882ea385c3cd904baed251ce
manager: conda
name: verilator
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.020-h7cd9344_0.conda
version: '5.020'
url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.022-h7cd9344_0.conda
version: '5.022'
- category: main
dependencies:
python: '>=2.6'
@@ -2069,27 +2070,27 @@ package:
python: '>=3.8'
zipp: '>=0.5'
hash:
md5: 746623a787e06191d80a2133e5daff17
sha256: e72d05f171f4567004c9360a838e9d5df21e23dcfeb945066b53a6e5f754b861
md5: b050a4bb0e90ebd6e7fa4093d6346867
sha256: 9a26136d2cc81ccac209d6ae24281ceba3365fe34e34b2c45570f2a96e9d9c1b
manager: conda
name: importlib-metadata
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-7.0.1-pyha770c72_0.conda
version: 7.0.1
url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-7.0.2-pyha770c72_0.conda
version: 7.0.2
- category: main
dependencies:
more-itertools: ''
python: '>=3.7'
hash:
md5: e9f79248d30e942f7c358ff21a1790f5
sha256: 14f5240c3834e1b784dd41a5a14392d9150dff62a74ae851f73e65d2e2bbd891
md5: c541ae264c9f1f21d83fc30dffb908ee
sha256: 232b40de8176fa7fb66a893653f8ae03c29616e04a83dae5a47df94b74e256ca
manager: conda
name: jaraco.classes
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/jaraco.classes-3.3.0-pyhd8ed1ab_0.conda
version: 3.3.0
url: https://conda.anaconda.org/conda-forge/noarch/jaraco.classes-3.3.1-pyhd8ed1ab_0.conda
version: 3.3.1
- category: main
dependencies:
markupsafe: '>=2.0'
@@ -2138,28 +2139,27 @@ package:
python: '>=3.10,<3.11.0a0'
python_abi: 3.10.* *_cp310
ruamel.yaml.clib: '>=0.1.2'
setuptools: ''
hash:
md5: 14fd49048b91c96a8fbf1113a8cc4f49
sha256: b31d4eb844d1b667a9cddf63eafa2c303049ae559098f88e403c2ab5ebdd274e
md5: 50b7d9b39099cdbabf65bf27df73a793
sha256: 37581cbd99eb8855b6d268c85d189d723dd4fa1f9d115b8a633bed6dea4c370e
manager: conda
name: ruamel.yaml
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.5-py310h2372a71_0.conda
version: 0.18.5
url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.6-py310h2372a71_0.conda
version: 0.18.6
- category: main
dependencies:
typing_extensions: 4.9.0 pyha770c72_0
typing_extensions: 4.10.0 pyha770c72_0
hash:
md5: c16524c1b7227dc80b36b4fa6f77cc86
sha256: d795c1eb1db4ea147f01ece74e5a504d7c2e8d5ee8c11ec987884967dd938f9c
md5: 091683b9150d2ebaa62fd7e2c86433da
sha256: 0698fe2c4e555fb44c27c60f7a21fa0eea7f5bf8186ad109543c5b056e27f96a
manager: conda
name: typing-extensions
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.9.0-hd8ed1ab_0.conda
version: 4.9.0
url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.10.0-hd8ed1ab_0.conda
version: 4.10.0
- category: main
dependencies:
brotli-python: '>=1.0.9'
@@ -2181,14 +2181,14 @@ package:
platformdirs: <5,>=3.9.1
python: '>=3.8'
hash:
md5: c119653cba436d8183c27bf6d190e587
sha256: 50827c3721a9dbf973b568709d4381add2a6552fa562f26a385c5edc16a534af
md5: 8797a4e26be36880a603aba29c785352
sha256: 1ced4445cf72cd9dc344ad04bdaf703a08cc428c8c46e4bda928ad79786ee153
manager: conda
name: virtualenv
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.0-pyhd8ed1ab_0.conda
version: 20.25.0
url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.1-pyhd8ed1ab_0.conda
version: 20.25.1
- category: main
dependencies:
libgcc-ng: '>=9.3.0'
@@ -2222,18 +2222,18 @@ package:
dependencies:
cffi: '>=1.12'
libgcc-ng: '>=12'
openssl: '>=3.1.5,<4.0a0'
openssl: '>=3.2.1,<4.0a0'
python: '>=3.10,<3.11.0a0'
python_abi: 3.10.* *_cp310
hash:
md5: a3618d82bb211dd03679a872cad533f2
sha256: 934249875c75779fd553aff568f25bdd625f5ba69cc8d60e78c847f35008e973
md5: 47e6ea7109182e9e48f8c5839f1bded7
sha256: eb514beb1c96969ebd299bb1979d6ccbf78087eb2a3772c364b94f778b8326ec
manager: conda
name: cryptography
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.2-py310hb8475ec_0.conda
version: 42.0.2
url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.5-py310h75e40e8_0.conda
version: 42.0.5
- category: main
dependencies:
curl: ''
@@ -2242,18 +2242,18 @@ package:
libgcc-ng: '>=12'
libiconv: '>=1.17,<2.0a0'
libzlib: '>=1.2.13,<1.3.0a0'
openssl: '>=3.2.0,<4.0a0'
pcre2: '>=10.42,<10.43.0a0'
openssl: '>=3.2.1,<4.0a0'
pcre2: '>=10.43,<10.44.0a0'
perl: 5.*
hash:
md5: 851970792301b407ba4c35e75e796791
sha256: 73a065e160d759e8fb0b169e615955a8fe0c148ed00c7f6ddf076f2e4adfd765
md5: 6817894081347566c0f097216bb36faa
sha256: 3ca58462b1c79a288587f8bdb82aa55829586e3f1635650988ab95d845b1b68e
manager: conda
name: git
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/git-2.43.0-pl5321h7bc287a_0.conda
version: 2.43.0
url: https://conda.anaconda.org/conda-forge/linux-64/git-2.44.0-pl5321h709897a_0.conda
version: 2.44.0
- category: main
dependencies:
cairo: '>=1.18.0,<2.0a0'
@@ -2274,16 +2274,16 @@ package:
version: 8.3.0
- category: main
dependencies:
importlib-metadata: '>=7.0.1,<7.0.2.0a0'
importlib-metadata: '>=7.0.2,<7.0.3.0a0'
hash:
md5: 4a2f43a20fa404b998859c6a470ba316
sha256: bc362df1d4f5a04c38dff29cd9c2d0ac584f9c4b45d3e4683ee090944a38fba4
md5: d11132727a247f2c1998779a2af743a1
sha256: b250e6a3e741b762bb2caf05119feb6245cb41b468542e5a9263cd01671098f7
manager: conda
name: importlib_metadata
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.1-hd8ed1ab_0.conda
version: 7.0.1
url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.2-hd8ed1ab_0.conda
version: 7.0.2
- category: main
dependencies:
libgcc-ng: '>=12'
@@ -2291,14 +2291,14 @@ package:
python_abi: 3.10.* *_cp310
typing-extensions: '>=4.6.0,!=4.7.0'
hash:
md5: 1a6153b4a9a54c7250c163bcc0c1ac66
sha256: 1e491ddbfd53a67f0734fb3f4ccd8782c24935549c281cf5a9bcf9c5ce8b9ec4
md5: 3f7aa5bfda188d57c4741de6fcc15330
sha256: 0048a136343af983b6f6ee9fc6a65259d231eb3e90c57b2f9adaef725b64b17e
manager: conda
name: pydantic-core
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.2-py310hcb5633a_0.conda
version: 2.16.2
url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.3-py310hcb5633a_0.conda
version: 2.16.3
- category: main
dependencies:
certifi: '>=2017.4.17'
@@ -2365,7 +2365,7 @@ package:
version: 1.4.4
- category: main
dependencies:
alsa-lib: '>=1.2.10,<1.2.11.0a0'
alsa-lib: '>=1.2.10,<1.3.0.0a0'
fontconfig: '>=2.14.2,<3.0a0'
fonts-conda-ecosystem: ''
freetype: '>=2.12.1,<3.0a0'
@@ -2396,18 +2396,18 @@ package:
- category: main
dependencies:
annotated-types: '>=0.4.0'
pydantic-core: 2.16.2
pydantic-core: 2.16.3
python: '>=3.7'
typing-extensions: '>=4.6.1'
hash:
md5: 3b1698c91820d852d802fc21471f52d8
sha256: 27083637287bb08a93e28616b5030f5eab31deb83d16fc132901ada987a62cfa
md5: 4f4e78b41c489b89d98719fcbde09361
sha256: 7367461b8f9e309f20f129605daa78635a1daa2538fe0b40d7f7238f8d430a29
manager: conda
name: pydantic
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.1-pyhd8ed1ab_0.conda
version: 2.6.1
url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.3-pyhd8ed1ab_0.conda
version: 2.6.3
- category: main
dependencies:
cryptography: ''
@@ -2447,14 +2447,14 @@ package:
python_abi: 3.10.* *_cp310
secretstorage: '>=3.2'
hash:
md5: e710fd8e57356a64cace034413da9cb3
sha256: 886a764e4bc2cfaabf2ea0a98461fbd526affd99c984a2789770eca43dd17c9b
md5: 441009e6f4fa93552a32d2ed40d332b4
sha256: 8187362ec306c92e3d8ebb51677fffb2e44cd0a6e013ed1c4ef439f1d2e5e06b
manager: conda
name: keyring
optional: false
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.0-py310hff52083_0.conda
version: 24.3.0
url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.1-py310hff52083_0.conda
version: 24.3.1
- category: main
dependencies:
__unix: ''

865
conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml generated
View File

File diff suppressed because it is too large Load Diff

2
conda-reqs/riscv-tools.yaml
View File

@@ -15,4 +15,4 @@ dependencies:
# https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
# documentation on package_spec syntax for constraining versions
- riscv-tools==1.0.3 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
- riscv-tools==1.0.6 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock

8
docs/Chipyard-Basics/Initial-Repo-Setup.rst
View File

@@ -15,8 +15,8 @@ Running on AWS EC2 with FireSim
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If you plan on using Chipyard alongside FireSim on AWS EC2 instances, you should refer to the :fsim_doc:`FireSim documentation <>`.
Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Initial-Setup/index.html>`
section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/index.html>`
section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
At that point, instead of cloning FireSim you can clone Chipyard by following :ref:`Chipyard-Basics/Initial-Repo-Setup:Setting up the Chipyard Repo`.
Default Requirements Installation
@@ -90,7 +90,9 @@ Run the following script based off which compiler you would like to use.
``-s 9`` skips pre-compiling FireMarshal default buildroot Linux sources
``-s 10`` skips running repository clean-up
``-s 10`` skips installing CIRCT
``-s 11`` skips running repository clean-up
.. code-block:: shell

10
docs/Simulation/FPGA-Accelerated-Simulation.rst
View File

@@ -26,12 +26,14 @@ Finally, source the following environment at the root of the FireSim directory:
cd sims/firesim
# (Recommended) The default manager environment (includes env.sh)
source sourceme-manager.sh
source sourceme-manager.sh`
# Completing setup using the manager
firesim managerinit --platform f1
.. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh``
At this point you're ready to use FireSim with Chipyard. If you're not already
familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
and proceed with the rest of the tutorial.
Running your Design in FireSim
@@ -47,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments:
The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme.
After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomV3Config`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomV3Config``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments.
We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``.
@@ -59,3 +61,5 @@ We are using the same target (top) RTL, and only need to specify a new set of co
:end-before: DOC include end: firesimconfig
While this option seems to require the maintenance of additional configuration code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``)
For more information on how to build your own hardware design on FireSim, please refer to :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Building-a-FireSim-AFI.html#building-your-own-hardware-designs-firesim-amazon-fpga-images>`.

2
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
View File

@@ -282,7 +282,7 @@ SRAM macros by default, but this feature does not exist yet.
VLSI Flow Control
^^^^^^^^^^^^^^^^^
Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action.
First, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action.
.. code-block:: shell

2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: 93004b7bd0...6019bb3508

5
fpga/src/main/resources/vcu118/sdboot/Makefile
View File

@@ -5,12 +5,13 @@ BUILD_DIR := $(ROOT_DIR)/build
CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump
CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles
CFLAGS=-march=rv64ima_zicsr_zifencei -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles
CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0
CFLAGS+= -I $(ROOT_DIR)/include -I.
LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds
PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden
# default to 1MHz but really should be overridden
PBUS_CLK ?= 1000000
default: elf bin dump

2
fpga/src/main/scala/arty/HarnessBinders.scala
View File

@@ -5,7 +5,7 @@ import chisel3._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
import freechips.rocketchip.jtag.{JTAGIO}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}

5
fpga/src/main/scala/arty100t/Configs.scala
View File

@@ -5,7 +5,8 @@ import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
@@ -58,5 +59,5 @@ class NoCoresArty100TConfig extends Config(
class BringupArty100TConfig extends Config(
new WithArty100TSerialTLToGPIO ++
new WithArty100TTweaks(freqMHz = 50) ++
new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++
new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialPhyParams(freqMHz=50)) ++
new chipyard.ChipBringupHostConfig)

31
fpga/src/main/scala/arty100t/HarnessBinders.scala
View File

@@ -5,10 +5,9 @@ import chisel3._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.shell._
@@ -61,10 +60,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
harnessIO <> port.io
harnessIO match {
case io: DecoupledSerialIO => {
case io: DecoupledPhitIO => {
val clkIO = io match {
case io: InternalSyncSerialIO => IOPin(io.clock_out)
case io: ExternalSyncSerialIO => IOPin(io.clock_in)
case io: InternalSyncPhitIO => IOPin(io.clock_out)
case io: ExternalSyncPhitIO => IOPin(io.clock_in)
}
val packagePinsWithPackageIOs = Seq(
("G13", clkIO),
@@ -72,14 +71,14 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
("A11", IOPin(io.out.ready)),
("D12", IOPin(io.in.valid)),
("D13", IOPin(io.in.ready)),
("B18", IOPin(io.out.bits, 0)),
("A18", IOPin(io.out.bits, 1)),
("K16", IOPin(io.out.bits, 2)),
("E15", IOPin(io.out.bits, 3)),
("E16", IOPin(io.in.bits, 0)),
("D15", IOPin(io.in.bits, 1)),
("C15", IOPin(io.in.bits, 2)),
("J17", IOPin(io.in.bits, 3))
("B18", IOPin(io.out.bits.phit, 0)),
("A18", IOPin(io.out.bits.phit, 1)),
("K16", IOPin(io.out.bits.phit, 2)),
("E15", IOPin(io.out.bits.phit, 3)),
("E16", IOPin(io.in.bits.phit, 0)),
("D15", IOPin(io.in.bits.phit, 1)),
("C15", IOPin(io.in.bits.phit, 2)),
("J17", IOPin(io.in.bits.phit, 3))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addPackagePin(io, pin)
@@ -88,10 +87,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
// Don't add IOB to the clock, if its an input
io match {
case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
}

2
fpga/src/main/scala/nexysvideo/Configs.scala
View File

@@ -5,7 +5,7 @@ import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.system._
import freechips.rocketchip.tile._

1
fpga/src/main/scala/nexysvideo/HarnessBinders.scala
View File

@@ -7,6 +7,7 @@ import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import sifive.blocks.devices.uart.{UARTParams}

2
fpga/src/main/scala/vc707/Configs.scala
View File

@@ -72,7 +72,7 @@ class RocketVC707Config extends Config (
class BoomVC707Config extends Config (
new WithFPGAFrequency(50) ++
new WithVC707Tweaks ++
new chipyard.MegaBoomConfig
new chipyard.MegaBoomV3Config
)
class WithFPGAFrequency(fMHz: Double) extends Config (

4
fpga/src/main/scala/vc707/HarnessBinders.scala
View File

@@ -3,10 +3,10 @@ package chipyard.fpga.vc707
import chisel3._
import chisel3.experimental.{BaseModule}
import freechips.rocketchip.util.{HeterogeneousBag}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.uart.{UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO}

4
fpga/src/main/scala/vcu118/Configs.scala
View File

@@ -54,11 +54,11 @@ class WithVCU118Tweaks extends Config(
new WithUART ++
new WithSPISDCard ++
new WithDDRMem ++
new WithJTAG ++
// other configuration
new WithDefaultPeripherals ++
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
)
@@ -72,7 +72,7 @@ class RocketVCU118Config extends Config(
class BoomVCU118Config extends Config(
new WithFPGAFrequency(50) ++
new WithVCU118Tweaks ++
new chipyard.MegaBoomConfig
new chipyard.MegaBoomV3Config
)
class WithFPGAFrequency(fMHz: Double) extends Config(

18
fpga/src/main/scala/vcu118/HarnessBinders.scala
View File

@@ -3,10 +3,10 @@ package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{BaseModule}
import freechips.rocketchip.util.{HeterogeneousBag}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.uart.{UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import chipyard._
@@ -36,3 +36,17 @@ class WithDDRMem extends HarnessBinder({
ddrClientBundle <> port.io
}
})
class WithJTAG extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
port.io.TCK := jtag_io.TCK
port.io.TMS := jtag_io.TMS
port.io.TDI := jtag_io.TDI
jtag_io.TDO.data := port.io.TDO
jtag_io.TDO.driven := true.B
// ignore srst_n
jtag_io.srst_n := DontCare
}
})

3
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -85,6 +85,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
)))))
ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
/*** JTAG ***/
val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())
// module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this)
}

2
generators/boom

Submodule generators/boom updated: 9459af0c1f...506c11c99c

12
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -19,9 +19,11 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
@@ -43,12 +45,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l)
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop

10
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -20,9 +20,6 @@ import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
@@ -92,7 +89,8 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
{
def coreMonitorBundles = totalTiles.values.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle
case b: boom.v3.common.BoomTile => b.module.core.coreMonitorBundle
case b: boom.v4.common.BoomTile => b.module.core.coreMonitorBundle
}.toList
// No-tile configs have to be handled specially.
@@ -132,6 +130,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
}
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasHierarchicalElementsRootContextModuleImp
{
with HasHierarchicalElementsRootContextModuleImp {
override lazy val outer = _outer
}

19
generators/chipyard/src/main/scala/System.scala
View File

@@ -38,7 +38,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
/**
* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
class ChipyardSystemModule(_outer: ChipyardSystem) extends ChipyardSubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with DontTouch
@@ -60,6 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
private val portName = "tl_mem"
private val device = new MemoryDevice
private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
private val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(locateTLBusWrapper(SBUS))
val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
Seq.tabulate(nMemoryChannels) { channel =>
@@ -76,15 +77,15 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
supportsPutFull = TransferSizes(1, mbus.blockBytes),
supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
beatBytes = memPortParams.beatBytes)
}
}).toList.flatten)
}
}).toList.flatten)
mbus.coupleTo(s"memory_controller_port_named_$portName") {
(memTLNode
:*= TLBuffer()
:*= TLSourceShrinker(1 << idBits)
:*= TLWidthWidget(mbus.beatBytes)
:*= _)
mbus.coupleTo(s"memory_controller_port_named_$portName") {
(memTLNode
:*= TLBuffer()
:*= TLSourceShrinker(1 << idBits)
:*= TLWidthWidget(mbus.beatBytes)
:*= _)
}
val mem_tl = InModuleBody { memTLNode.makeIOs() }

165
generators/chipyard/src/main/scala/config/AbstractConfig.scala
View File

@@ -11,24 +11,32 @@ import org.chipsalliance.cde.config.{Config}
// --------------
class AbstractConfig extends Config(
// ================================================
// Set up TestHarness
// ================================================
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM
new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed
new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
new chipyard.harness.WithDriveChipIdPin ++ // drive chip id pin from harness binder, if chip id pin is present
new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port
new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
new chipyard.harness.WithUARTAdapter ++ /** add UART adapter to display UART on stdout, if uart is present */
new chipyard.harness.WithBlackBoxSimMem ++ /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */
new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */
new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */
new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */
new chipyard.harness.WithGPIOPinsTiedOff ++ /** tie-off chiptop GPIO-pins, if GPIO-punchthrough is used */
new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */
new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */
new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */
new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */
new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */
new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
new chipyard.harness.WithDriveChipIdPin ++ /** drive chip id pin from harness binder, if chip id pin is present */
new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */
new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
// ================================================
// Set up I/O cells + punch I/Os in ChipTop
// ================================================
// The IOBinders instantiate ChipTop IOs to match desired digital IOs
// IOCells are generated for "Chip-like" IOs
new chipyard.iobinders.WithSerialTLIOCells ++
@@ -53,42 +61,99 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++
new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
// ================================================
// Set up External Memory and IO Devices
// ================================================
// External memory section
new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes
client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
)
)) ++
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */
new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */
// MMIO device section
new chipyard.config.WithUART ++ /** add a UART */
// ================================================
// Set up Debug/Bringup/Testing Features
// ================================================
// JTAG
new freechips.rocketchip.subsystem.WithDebugSBA ++ /** enable the SBA (system-bus-access) feature of the debug module */
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data word capacity */
new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */
// Boot Select Pins
new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */
new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */
// ================================================
// Set up Interrupts
// ================================================
// CLINT and PLIC related settings goes here
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */
// ================================================
// Set up Tiles
// ================================================
// tile-local settings goes here
// ================================================
// Set up Memory system
// ================================================
// On-chip memory section
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */
new chipyard.config.WithBootROM ++ /** use default bootrom */
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */
size = 64 * 1024) ++
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
// Coherency settings
new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence */
// Bus/interconnect settings
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */
// ================================================
// Set up power, reset and clocking
// ================================================
// ChipTop clock IO/PLL/Divider/Mux settings
new chipyard.clocking.WithClockTapIOCells ++ /** Default generate a clock tapio */
new chipyard.clocking.WithPassthroughClockGenerator ++
// DigitalTop-internal clocking settings
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */
new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */
new chipyard.config.WithControlBusFrequency(500.0) ++ /** Default 500 MHz cbus */
new chipyard.config.WithSystemBusFrequency(500.0) ++ /** Default 500 MHz sbus */
new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */
new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */
new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */
new chipyard.config.WithNoSubsystemClockIO ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
// reset
// power
// ==================================
// Base Settings
// ==================================
new freechips.rocketchip.system.BaseConfig /** "base" rocketchip system */
)

100
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -3,60 +3,116 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
// ---------------------
// BOOM Configs
// BOOM V3 Configs
// Performant, stable baseline
// ---------------------
class SmallBoomConfig extends Config(
new boom.common.WithNSmallBooms(1) ++ // small boom config
class SmallBoomV3Config extends Config(
new boom.v3.common.WithNSmallBooms(1) ++ // small boom config
new chipyard.config.AbstractConfig)
class MediumBoomConfig extends Config(
new boom.common.WithNMediumBooms(1) ++ // medium boom config
class MediumBoomV3Config extends Config(
new boom.v3.common.WithNMediumBooms(1) ++ // medium boom config
new chipyard.config.AbstractConfig)
class LargeBoomConfig extends Config(
new boom.common.WithNLargeBooms(1) ++ // large boom config
class LargeBoomV3Config extends Config(
new boom.v3.common.WithNLargeBooms(1) ++ // large boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MegaBoomConfig extends Config(
new boom.common.WithNMegaBooms(1) ++ // mega boom config
class MegaBoomV3Config extends Config(
new boom.v3.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class DualSmallBoomConfig extends Config(
new boom.common.WithNSmallBooms(2) ++ // 2 boom cores
class DualSmallBoomV3Config extends Config(
new boom.v3.common.WithNSmallBooms(2) ++ // 2 boom cores
new chipyard.config.AbstractConfig)
class Cloned64MegaBoomConfig extends Config(
new boom.common.WithCloneBoomTiles(63, 0) ++
new boom.common.WithNMegaBooms(1) ++ // mega boom config
class Cloned64MegaBoomV3Config extends Config(
new boom.v3.common.WithCloneBoomTiles(63, 0) ++
new boom.v3.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class LoopbackNICLargeBoomConfig extends Config(
class LoopbackNICLargeBoomV3Config extends Config(
new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback
new icenet.WithIceNIC ++ // build a NIC
new boom.common.WithNLargeBooms(1) ++
new boom.v3.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomCosimConfig extends Config(
class MediumBoomV3CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNMediumBooms(1) ++
new boom.v3.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomConfig extends Config(
class dmiMediumBoomV3Config extends Config(
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.common.WithNMediumBooms(1) ++
new boom.v3.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomCosimConfig extends Config(
class dmiMediumBoomV3CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anythint to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.common.WithNMediumBooms(1) ++
new boom.v3.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
// ---------------------
// BOOM V4 Configs
// Less stable and performant, but with more advanced micro-architecture
// Use for PD exploration
// ---------------------
class SmallBoomV4Config extends Config(
new boom.v4.common.WithNSmallBooms(1) ++ // small boom config
new chipyard.config.AbstractConfig)
class MediumBoomV4Config extends Config(
new boom.v4.common.WithNMediumBooms(1) ++ // medium boom config
new chipyard.config.AbstractConfig)
class LargeBoomV4Config extends Config(
new boom.v4.common.WithNLargeBooms(1) ++ // large boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MegaBoomV4Config extends Config(
new boom.v4.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class DualSmallBoomV4Config extends Config(
new boom.v4.common.WithNSmallBooms(2) ++ // 2 boom cores
new chipyard.config.AbstractConfig)
class Cloned64MegaBoomV4Config extends Config(
new boom.v4.common.WithCloneBoomTiles(63, 0) ++
new boom.v4.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomV4CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.v4.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomV4Config extends Config(
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.v4.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomV4CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anythint to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.v4.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)

6
generators/chipyard/src/main/scala/config/ChipConfigs.scala
View File

@@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config(
isMemoryDevice = true
)),
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock
))) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
@@ -77,8 +77,8 @@ class ChipBringupHostConfig extends Config(
size = BigInt("80000000", 16)
))
)),
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
))) ++
//============================

50
generators/chipyard/src/main/scala/config/ChipletConfigs.scala
View File

@@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config(
new testchipip.serdes.WithSerialTL(Seq(
testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga
client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client
phyParams = testchipip.serdes.ExternalSyncSerialParams() // bringup serial-tl is sync'd to external clock
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock
),
testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client
@@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config(
)),
slaveWhere = OBUS
)),
phyParams = testchipip.serdes.SourceSyncSerialParams() // chip-to-chip serial-tl is symmetric source-sync'd
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
))
) ++
new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory
@@ -45,3 +45,49 @@ class MultiSimSymmetricChipletRocketConfig extends Config(
new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
)
// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet
class RocketCoreChipletConfig extends Config(
new testchipip.serdes.WithSerialTL(Seq(
testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams()),
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
),
testchipip.serdes.SerialTLParams(
manager = Some(testchipip.serdes.SerialTLManagerParams(
cohParams = Seq(testchipip.serdes.ManagerCOHParams(
address = BigInt("80000000", 16),
size = BigInt("100000000", 16)
)),
slaveWhere = OBUS,
isMemoryDevice = true
)),
phyParams = testchipip.serdes.SourceSyncSerialPhyParams()
)
)) ++
new testchipip.soc.WithOffchipBusClient(SBUS) ++
new testchipip.soc.WithOffchipBus ++
new testchipip.soc.WithNoScratchpads ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// LLC-only chiplet
class LLCChipletConfig extends Config(
new chipyard.harness.WithSerialTLTiedOff ++
new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)),
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
))) ++
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
new chipyard.NoCoresConfig
)
class MultiSimLLCChipletRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++
new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++
new chipyard.harness.WithMultiChip(1, new LLCChipletConfig)
)

14
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config}
// ---------------------
class LargeBoomAndRocketConfig extends Config(
new boom.common.WithNLargeBooms(1) ++ // single-core boom
new boom.v3.common.WithNLargeBooms(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -16,7 +16,7 @@ class LargeBoomAndRocketConfig extends Config(
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
new boom.common.WithNLargeBooms(1) ++ // add 1 boom core
new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -26,7 +26,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket)
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
new boom.common.WithNLargeBooms(1) ++ // add 1 boom core
new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -36,21 +36,21 @@ class DualLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket)
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include end: DualBoomAndRocketOneHwacha
class DualLargeBoomAndDualRocketConfig extends Config(
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // add 2 rocket cores
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include start: DualBoomAndSingleRocket
class DualLargeBoomAndSingleRocketConfig extends Config(
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -58,7 +58,7 @@ class DualLargeBoomAndSingleRocketConfig extends Config(
class LargeBoomAndRocketWithControlCoreConfig extends Config(
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
new boom.common.WithNLargeBooms(1) ++ // Add 1 boom core
new boom.v3.common.WithNLargeBooms(1) ++ // Add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)

1
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
View File

@@ -59,6 +59,7 @@ class LargeNVDLARocketConfig extends Config(
new chipyard.config.AbstractConfig)
class ManyMMIOAcceleratorRocketConfig extends Config(
new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero
new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO: hack around dontTouch not working in SFC
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough

10
generators/chipyard/src/main/scala/config/NoCConfigs.scala
View File

@@ -240,7 +240,7 @@ class SbusMeshNoCConfig extends Config(
"Core 9 " -> 13,
"Core 10 " -> 14,
"Core 11 " -> 15,
"serial-tl" -> 0),
"serial_tl" -> 0),
outNodeMapping = ListMap(
"system[0]" -> 5,
"system[1]" -> 6,
@@ -251,14 +251,16 @@ class SbusMeshNoCConfig extends Config(
topology = Mesh2D(4, 4),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1),
),
beNoCParams = NoCParams(
topology = Mesh2D(4, 4),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1),
),
beDivision = 4
)) ++
), inlineNoC = true) ++
new freechips.rocketchip.subsystem.WithNBigCores(12) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++

1
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -75,6 +75,7 @@ class ManyPeripheralsRocketConfig extends Config(
new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new chipyard.config.WithPeripheryTimer ++ // add the pwm timer device
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port

15
generators/chipyard/src/main/scala/config/RadianceConfigs.scala
View File

@@ -5,10 +5,8 @@ import chipyard.stage.phases.TargetDirKey
import freechips.rocketchip.devices.tilelink.BootROMLocated
import freechips.rocketchip.diplomacy.{AsynchronousCrossing, BigIntHexContext}
import freechips.rocketchip.subsystem.{InCluster, WithCluster, WithExtMemSize}
import freechips.rocketchip.tile.XLen
import org.chipsalliance.cde.config.Config
import radiance.memory._
import radiance.subsystem.WithRadianceGemmini
class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => {
case RadianceROMsLocated() => Some(up(RadianceROMsLocated()).getOrElse(Seq()) ++
@@ -45,11 +43,12 @@ class RadianceBaseConfig(argsBinFilename: String = "args.bin") extends Config(
new WithRadROMs(0x40000L, 0x20000, "sims/op_b.bin") ++
new chipyard.harness.WithCeaseSuccess ++
new chipyard.iobinders.WithCeasePunchThrough ++
new radiance.subsystem.WithRadianceSimParams(true) ++
new AbstractConfig)
class RadianceConfig extends Config(
// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
// new WithRadianceGemmini(location = InCluster(0), dim = 8, extMemBase = x"ff000000", spSizeInKB = 16, accSizeInKB = 8) ++
// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, extMemBase = x"ff000000", spSizeInKB = 16, accSizeInKB = 8) ++
new radiance.subsystem.WithRadianceCores(1, location=InCluster(0), useVxCache = false) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++
@@ -57,8 +56,8 @@ class RadianceConfig extends Config(
new RadianceBaseConfig)
class RadianceClusterConfig extends Config(
// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
// new WithRadianceGemmini(location = InCluster(0), dim = 8, extMemBase = x"ff000000", spSizeInKB = 16, accSizeInKB = 8) ++
// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, extMemBase = x"ff000000", spSizeInKB = 16, accSizeInKB = 8) ++
new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
@@ -86,6 +85,10 @@ class RadianceClusterConfig2 extends Config(
new radiance.subsystem.WithRadianceCluster(0) ++
new RadianceBaseConfig("args.2.bin"))
class RadianceClusterSynConfig extends Config(
new radiance.subsystem.WithRadianceSimParams(false) ++
new RadianceClusterConfig)
class RadianceGemminiConfig extends Config(
new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++

4
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
View File

@@ -50,10 +50,10 @@ class MempressRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class HwachaLargeBoomConfig extends Config(
class HwachaLargeBoomV3Config extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new boom.common.WithNLargeBooms(1) ++
new boom.v3.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)

9
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
View File

@@ -18,7 +18,8 @@ class dmiSpikeConfig extends Config(
// Avoids polling on the UART registers
class SpikeFastUARTConfig extends Config(
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.AbstractConfig)
@@ -27,7 +28,8 @@ class SpikeFastUARTConfig extends Config(
class SpikeUltraFastConfig extends Config(
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++
@@ -47,7 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config(
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++

9
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -32,8 +32,13 @@ class NonBlockingTraceGenConfig extends Config(
new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new AbstractTraceGenConfig)
class BoomTraceGenConfig extends Config(
new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
class BoomV3TraceGenConfig extends Config(
new tracegen.WithBoomV3TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new AbstractTraceGenConfig)
class BoomV4TraceGenConfig extends Config(
new tracegen.WithBoomV4TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new AbstractTraceGenConfig)

2
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -32,7 +32,7 @@ class TutorialStarterConfig extends Config(
// Uncomment out one (or multiple) of the lines below, and choose
// how many cores you want.
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores
// new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
// new boom.v3.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
// CUSTOMIZE the L2
// Uncomment this line, and specify a size if you want to have a L2

10
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -16,6 +16,7 @@ import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.timer._
import testchipip._
@@ -65,11 +66,12 @@ class WithNoUART extends Config((site, here, up) => {
* @param address the address of the UART device
* @param baudrate the baudrate of the UART device
*/
class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000) extends Config ((site, here, up) => {
class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000, txEntries: Int = 8, rxEntries: Int = 8) extends Config ((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq(
UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
UARTParams(address = address, nTxEntries = txEntries, nRxEntries = rxEntries, initBaudRate = baudrate))
})
// @deprecated("Use WithUART instead of WithUARTFIFOEntries", "chipyard v1.10")
class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
})
@@ -168,3 +170,7 @@ class WithNoBusErrorDevices extends Config((site, here, up) => {
case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None)
case FrontBusKey => up(FrontBusKey).copy(errorDevice = None)
})
class WithPeripheryTimer(timerParams: TimerParams = TimerParams(0x4000)) extends Config((site, here, up) => {
case PeripheryTimerKey => Seq(timerParams)
})

46
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -5,9 +5,8 @@ import chisel3._
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, PgLevels}
import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams}
import sodor.common.{SodorTileAttachParams}
import ibex.{IbexTileAttachParams}
@@ -18,7 +17,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case other => other
}
@@ -26,7 +27,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
class WithTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = true)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = true)))
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true))
@@ -37,7 +40,9 @@ class WithTraceIO extends Config((site, here, up) => {
class WithNoTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = false)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = false)))
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = false))
@@ -50,7 +55,9 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case other => other
}
@@ -60,7 +67,9 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPMPs = n)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPMPs = n)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPMPs = n)))
case other => other
}
@@ -95,7 +104,9 @@ class WithTilePrefetchers extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
@@ -108,10 +119,15 @@ class WithTilePrefetchers extends Config((site, here, up) => {
// Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
// This typically makes it easier to close timing
class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
boundaryBuffers=buffers
))
}
})
class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
boundaryBuffers=buffers
))
}
})
// Uses SV48 if possible, otherwise default to the Rocket Chip core default
class WithSV48IfPossible extends Config((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
})

4
generators/chipyard/src/main/scala/example/CustomChipTop.scala
View File

@@ -67,13 +67,13 @@ class WithCustomChipTop extends Config((site, here, up) => {
})
class WithBrokenOutUARTIO extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
(system: HasPeripheryUART) => {
val uart_txd = IO(Output(Bool()))
val uart_rxd = IO(Input(Bool()))
system.uart(0).rxd := uart_rxd
uart_txd := system.uart(0).txd
val where = PBUS // TODO fix
val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(Seq(UARTPort(() => {
val uart_wire = Wire(new UARTPortIO(system.uart(0).c))

2
generators/chipyard/src/main/scala/example/FlatChipTop.scala
View File

@@ -145,7 +145,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
// UART
//==========================
require(system.uarts.size == 1)
val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.uart.head, "uart_0", p(IOCellKey))
val where = PBUS // TODO fix
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000

10
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
View File

@@ -47,16 +47,16 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// Figure out which clock drives the harness TLSerdes, based on the port type
val serial_ram_clock = dut.serial_tl_pad match {
case io: InternalSyncSerialIO => io.clock_out
case io: ExternalSyncSerialIO => clock
case io: InternalSyncPhitIO => io.clock_out
case io: ExternalSyncPhitIO => clock
}
dut.serial_tl_pad match {
case io: ExternalSyncSerialIO => io.clock_in := clock
case io: InternalSyncSerialIO =>
case io: ExternalSyncPhitIO => io.clock_in := clock
case io: InternalSyncPhitIO =>
}
dut.serial_tl_pad match {
case pad: DecoupledSerialIO => {
case pad: DecoupledPhitIO => {
withClockAndReset(serial_ram_clock, reset) {
// SerialRAM implements the memory regions the chip expects
val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)

4
generators/chipyard/src/main/scala/example/GCD.scala
View File

@@ -5,7 +5,7 @@ import chisel3.util._
import chisel3.experimental.{IntParam, BaseModule}
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
@@ -194,6 +194,8 @@ class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends
trait CanHavePeripheryGCD { this: BaseSubsystem =>
private val portName = "gcd"
private val pbus = locateTLBusWrapper(PBUS)
// Only build if we are using the TL (nonAXI4) version
val gcd_busy = p(GCDKey) match {
case Some(params) => {

5
generators/chipyard/src/main/scala/example/InitZero.scala
View File

@@ -2,7 +2,7 @@ package chipyard.example
import chisel3._
import chisel3.util._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
import freechips.rocketchip.tilelink._
@@ -61,7 +61,8 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
implicit val p: Parameters
p(InitZeroKey) .map { k =>
val initZero = LazyModule(new InitZero()(p))
val fbus = locateTLBusWrapper(FBUS)
val initZero = fbus { LazyModule(new InitZero()(p)) }
fbus.coupleFrom("init-zero") { _ := initZero.node }
}
}

1
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
View File

@@ -199,6 +199,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
val streamingFIR = p(GenericFIRKey) match {
case Some(params) => {
val pbus = locateTLBusWrapper(PBUS)
val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
genIn = FixedPoint(8.W, 3.BP),

1
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
View File

@@ -131,6 +131,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => {
val pbus = locateTLBusWrapper(PBUS)
val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }

29
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -44,6 +44,14 @@ class HarnessBinder[T <: HasHarnessInstantiators, S <: Port[_]](
class WithGPIOTiedOff extends HarnessBinder({
case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => {
port.io <> AnalogConst(0)
}
})
class WithGPIOPinsTiedOff extends HarnessBinder({
case (th: HasHarnessInstantiators, port: GPIOPinsPort, chipId: Int) => {
port.io := DontCare
}
})
@@ -209,17 +217,17 @@ class WithTiedOffDMI extends HarnessBinder({
class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
port.io match {
case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
case io: SourceSyncSerialIO => {
case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
case io: SourceSyncPhitIO => {
io.clock_in := false.B.asClock
io.reset_in := false.B.asAsyncReset
io.in := DontCare
io.credit_in := DontCare
}
}
port.io match {
case io: InternalSyncSerialIO =>
case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
case io: InternalSyncPhitIO =>
case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock
case io: SourceSyncPhitIO =>
case _ =>
}
}
@@ -228,17 +236,18 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
class WithSimTSIOverSerialTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
port.io match {
case io: InternalSyncSerialIO =>
case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
case io: InternalSyncPhitIO =>
case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock
case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset
}
port.io match {
case io: DecoupledSerialIO => {
case io: DecoupledPhitIO => {
// If the port is locally synchronous (provides a clock), drive everything with that clock
// Else, drive everything with the harnes clock
val clock = port.io match {
case io: InternalSyncSerialIO => io.clock_out
case io: ExternalSyncSerialIO => th.harnessBinderClock
case io: InternalSyncPhitIO => io.clock_out
case io: ExternalSyncPhitIO => th.harnessBinderClock
}
withClock(clock) {
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)

12
generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
View File

@@ -59,25 +59,23 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
(p0: SerialTLPort) => p0.portId == chip0portId,
(p1: SerialTLPort) => p1.portId == chip1portId,
(th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = {
def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = {
clkSink.clock_in := clkSource.clock_out
clkSink.in <> clkSource.out
clkSource.in <> clkSink.out
}
def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = {
a.clock_in := b.clock_out
b.clock_in := a.clock_out
a.reset_in := b.reset_out
b.reset_in := a.reset_out
a.in := b.out
b.in := a.out
a.credit_in := b.credit_out
b.credit_in := a.credit_out
}
(p0.io, p1.io) match {
case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
case (io0: SourceSyncSerialIO , io1: SourceSyncSerialIO ) => connectSourceSyncSerialIO (io0, io1)
case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)
case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0)
case (io0: SourceSyncPhitIO , io1: SourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1)
}
}
)

41
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View File

@@ -5,7 +5,12 @@ import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import org.chipsalliance.diplomacy.aop._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
@@ -165,15 +170,17 @@ case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
class WithGPIOCells extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp) => {
(system: HasPeripheryGPIO) => {
val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val p = system.asInstanceOf[BaseSubsystem].p
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
pin.i.po.foreach(_ := DontCare)
iocell.io.pad <> g
(GPIOPort(() => g, i, j), iocell)
}).unzip
@@ -183,7 +190,7 @@ class WithGPIOCells extends OverrideIOBinder({
})
class WithGPIOPunchthrough extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp) => {
(system: HasPeripheryGPIO) => {
val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
io_gpio <> gpio
@@ -194,7 +201,7 @@ class WithGPIOPunchthrough extends OverrideIOBinder({
})
class WithI2CPunchthrough extends OverrideIOBinder({
(system: HasPeripheryI2CModuleImp) => {
(system: HasPeripheryI2C) => {
val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
io_i2c <> i2c
@@ -206,11 +213,12 @@ class WithI2CPunchthrough extends OverrideIOBinder({
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
(system: HasPeripheryUART) => {
val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
val p = system.asInstanceOf[BaseSubsystem].p
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix
val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
@@ -226,7 +234,7 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
val spi = system.asInstanceOf[BaseSubsystem].module.asInstanceOf[HasPeripherySPIBundle].spi
val spi = system.spi
val ports = spi.zipWithIndex.map({ case (s, i) =>
val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
io_spi <> s
@@ -238,20 +246,20 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
})
class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlashModuleImp) => {
(system: HasPeripherySPIFlash) => {
val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset)
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
@@ -260,7 +268,7 @@ class WithSPIFlashIOCells extends OverrideIOBinder({
iocell
}
(SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
(SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
@@ -418,7 +426,8 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
(system: CanHaveSlaveAXI4Port) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode)
val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
clockSinkNode.map(_ := fbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {

2
generators/chipyard/src/main/scala/iobinders/Ports.scala
View File

@@ -16,8 +16,8 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
import freechips.rocketchip.devices.debug.{ClockedDMIIO}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
trait Port[T <: Data] {
val getIO: () => T

2
generators/constellation

Submodule generators/constellation updated: 81f005ffea...6664839b10

1
generators/diplomacy Submodule

Submodule generators/diplomacy added at edf375300d

2
generators/fft-generator

Submodule generators/fft-generator updated: 4e7e6cbbbc...490b975d36

4
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import sifive.blocks.devices.uart._
import testchipip.serdes.{ExternalSyncSerialIO}
import testchipip.serdes.{ExternalSyncPhitIO}
import testchipip.tsi.{SerialRAM}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
@@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
case (th: FireSim, port: SerialTLPort, chipId: Int) => {
port.io match {
case io: ExternalSyncSerialIO => {
case io: ExternalSyncPhitIO => {
io.clock_in := th.harnessBinderClock
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
ram.io.ser.in <> io.out

6
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
import freechips.rocketchip.tile.{RocketTile}
import boom.common.{BoomTile}
import boom.v3.common.{BoomTile}
import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}
import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
@@ -112,10 +112,10 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
case b: BoomTile => {
val core = b.module.core
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case irf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
case frf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
}
}
case _ =>

32
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -107,7 +107,10 @@ class WithFireSimDesignTweaks extends Config(
// Optional: reduce the width of the Serial TL interface
new testchipip.serdes.WithSerialTLWidth(4) ++
// Required*: Scale default baud rate with periphery bus frequency
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new chipyard.config.WithUART(
baudrate=BigInt(3686400L),
txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
// Optional: Adds IO to attach tracerV bridges
new chipyard.config.WithTraceIO ++
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
@@ -201,7 +204,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new boom.v3.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new WithFireSimDesignTweaks
)
@@ -264,8 +267,8 @@ class FireSimSmallSystemConfig extends Config(
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32)
client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits = 4)),
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32)
))) ++
new testchipip.iceblk.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
@@ -273,13 +276,13 @@ class FireSimSmallSystemConfig extends Config(
new chipyard.RocketConfig)
//*****************************************************************
// Boom config, base off chipyard's LargeBoomConfig
// Boom config, base off chipyard's LargeBoomV3Config
//*****************************************************************
class FireSimLargeBoomConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LargeBoomConfig)
new chipyard.LargeBoomV3Config)
//********************************************************************
// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
@@ -335,11 +338,11 @@ class FireSimCVA6Config extends Config(
// - Requires MTModels and MCRams mixins as prefixes to the platform config
// - May require larger build instances or JVM memory footprints
//*********************************************************************************/
class FireSim16LargeBoomConfig extends Config(
class FireSim16LargeBoomV3Config extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new boom.common.WithNLargeBooms(16) ++
new boom.v3.common.WithNLargeBooms(16) ++
new chipyard.config.AbstractConfig)
class FireSimNoMemPortConfig extends Config(
@@ -360,3 +363,16 @@ class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config(
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LeanGemminiRocketConfig)
class FireSimRadianceClusterSynConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.RadianceClusterSynConfig)
class FireSimLargeBoomCospikeConfig extends Config(
new firesim.firesim.WithCospikeBridge ++
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks++
new chipyard.LargeBoomV3Config)

2
generators/gemmini

Submodule generators/gemmini updated: 4db2e1f534...493c45a8db

2
generators/mempress

Submodule generators/mempress updated: c3d4901ab0...415f55b583

2
generators/nvdla

Submodule generators/nvdla updated: 95697452e5...cfcb5fafcb

2
generators/radiance

Submodule generators/radiance updated: 824cae7c50...a915451d03

2
generators/rocc-acc-utils

Submodule generators/rocc-acc-utils updated: b001c888f9...9b8c5d375f

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 20ce83bfc1...8c8b3f5dcf

2
generators/rocket-chip-blocks

Submodule generators/rocket-chip-blocks updated: 3dddfe9f5b...2fc961f356

2
generators/sha3

Submodule generators/sha3 updated: 5e49347f06...2d38585d64

2
generators/shuttle

Submodule generators/shuttle updated: fd325d43a1...b75fada257

2
generators/testchipip

Submodule generators/testchipip updated: d83fcccda0...731d51ee15

43
generators/tracegen/src/main/scala/Configs.scala
View File

@@ -8,7 +8,6 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.BaseConfig
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
import boom.lsu._
import scala.math.{max, min}
class WithTraceGen(
@@ -50,7 +49,7 @@ class WithTraceGen(
case NumTiles => up(NumTiles) + n
})
class WithBoomTraceGen(
class WithBoomV3TraceGen(
n: Int = 2,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
@@ -61,8 +60,44 @@ class WithBoomTraceGen(
val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
BoomTraceGenTileAttachParams(
tileParams = BoomTraceGenParams(
boom.v3.lsu.BoomTraceGenTileAttachParams(
tileParams = boom.v3.lsu.BoomTraceGenParams(
tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val nSets = dcp.nSets
val nWays = dcp.nWays
val blockOffset = site(SystemBusKey).blockOffset
val nBeats = site(SystemBusKey).blockBeats
List.tabulate(nWays) { i =>
Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
}.flatten
},
maxRequests = nReqs,
memStart = memOffset,
numGens = params.size),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
class WithBoomV4TraceGen(
n: Int = 2,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
boom.v4.lsu.BoomTraceGenTileAttachParams(
tileParams = boom.v4.lsu.BoomTraceGenParams(
tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),

6
generators/tracegen/src/main/scala/System.scala
View File

@@ -6,7 +6,6 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with InstantiatesHierarchicalElements
@@ -20,10 +19,11 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
val tileStatusNodes = totalTiles.values.toSeq.collect {
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
case t: boom.v3.lsu.BoomTraceGenTile => t.statusNode.makeSink()
case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink()
}
lazy val fakeClockDomain = sbus.generateSynchronousDomain
lazy val fakeClockDomain = locateTLBusWrapper("sbus").generateSynchronousDomain
lazy val clintOpt = None
lazy val debugOpt = None

104
scripts/build-circt-from-source.sh Executable file
View File

@@ -0,0 +1,104 @@
#!/usr/bin/env bash
# exit script if any command fails
set -e
set -o pipefail
RDIR=$(git rev-parse --show-toplevel)
# get helpful utilities
source $RDIR/scripts/utils.sh
common_setup
# Allow user to override MAKE
[ -n "${MAKE:+x}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make)
readonly MAKE
usage() {
echo "usage: ${0}"
echo ""
echo "Options"
echo " --prefix -p PREFIX : Install destination."
echo " --help -h : Display this message"
exit "$1"
}
PREFIX=""
# getopts does not support long options, and is inflexible
while [ "$1" != "" ];
do
case $1 in
-h | -H | --help | help )
usage 3 ;;
-p | --prefix )
shift
PREFIX=$(realpath $1) ;;
* )
error "invalid option $1"
usage 1 ;;
esac
shift
done
if [ -z "$PREFIX" ] ; then
error "ERROR: Prefix not given."
exit 1
fi
echo "Cloning CIRCT"
(
cd $RDIR/tools
git submodule update --init --progress circt
)
echo "Cloning CIRCT/LLVM"
(
cd $RDIR/tools/circt
git submodule init
# The settings in circt/.gitmodules don't "stick", so force-set them here
git config submodule.llvm.shallow true
git config submodule.llvm.branch main
git submodule update --recommend-shallow --progress llvm
)
echo "Building CIRCT's LLVM/MLIR"
(
cd $RDIR/tools/circt
rm -rf llvm/build
mkdir llvm/build
cd llvm/build
cmake -G Ninja ../llvm \
-DLLVM_ENABLE_PROJECTS="mlir" \
-DLLVM_TARGETS_TO_BUILD="host" \
-DLLVM_ENABLE_ASSERTIONS=ON \
-DCMAKE_BUILD_TYPE=RELEASE \
-DCMAKE_EXPORT_COMPILE_COMMANDS=ON \
-DCMAKE_EXE_LINKER_FLAGS="-L$RDIR/.conda-env/lib"
ninja
)
echo "Building CIRCT"
(
cd $RDIR/tools/circt
rm -rf build
mkdir build
cd build
cmake -G Ninja .. \
-DMLIR_DIR=$RDIR/tools/circt/llvm/build/lib/cmake/mlir \
-DLLVM_DIR=$RDIR/tools/circt/llvm/build/lib/cmake/llvm \
-DLLVM_ENABLE_ASSERTIONS=ON \
-DCMAKE_BUILD_TYPE=RELEASE \
-DCMAKE_INSTALL_PREFIX=$PREFIX \
-DCMAKE_EXE_LINKER_FLAGS="-L$RDIR/.conda-env/lib"
ninja
)
echo "Installing CIRCT to $PREFIX"
(
cd $RDIR/tools/circt/build
ninja install
)

25
scripts/build-setup.sh
View File

@@ -39,6 +39,7 @@ usage() {
echo " --verbose -v : Verbose printout"
echo " --use-unpinned-deps -ud : Use unpinned conda environment"
echo " --use-lean-conda : Install a leaner version of the repository (Smaller conda env, no FireSim, no FireMarshal)"
echo " --build-circt : Builds CIRCT from source, instead of downloading the precompiled binary"
echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')."
echo " --skip-conda : Skip Conda initialization (step 1)"
@@ -60,6 +61,7 @@ VERBOSE_FLAG=""
USE_UNPINNED_DEPS=false
USE_LEAN_CONDA=false
SKIP_LIST=()
BUILD_CIRCT=false
# getopts does not support long options, and is inflexible
while [ "$1" != "" ];
@@ -75,6 +77,8 @@ do
--use-lean-conda)
USE_LEAN_CONDA=true
SKIP_LIST+=(4 6 7 8 9) ;;
--build-circt)
BUILD_CIRCT=true ;;
-ud | --use-unpinned-deps )
USE_UNPINNED_DEPS=true ;;
--skip | -s)
@@ -306,13 +310,20 @@ if run_step "10"; then
PREFIX=$RISCV
fi
git submodule update --init $CYDIR/tools/install-circt &&
$CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-f circt-full-shared-linux-x64.tar.gz \
-i $PREFIX \
-v version-file \
-x $CYDIR/conda-reqs/circt.json \
-g null
if [ "$BUILD_CIRCT" = true ] ; then
echo "Building CIRCT from source, and installing to $PREFIX"
$CYDIR/scripts/build-circt-from-source.sh --prefix $PREFIX
else
echo "Downloading CIRCT from nightly build"
git submodule update --init $CYDIR/tools/install-circt &&
$CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-f circt-full-static-linux-x64.tar.gz \
-i $PREFIX \
-v version-file \
-x $CYDIR/conda-reqs/circt.json \
-g null
fi
exit_if_last_command_failed
fi

3
scripts/build-toolchain-extra.sh
View File

@@ -84,7 +84,7 @@ cp -p "${SRCDIR}/riscv-isa-sim/build/libfesvr.a" "${RISCV}/lib/"
CLEANAFTERINSTALL=$OLDCLEANAFTERINSTALL
echo '==> Installing Proxy Kernel'
CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv${XLEN}-unknown-elf
CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv${XLEN}-unknown-elf --with-arch=rv64gc_zifencei
echo '==> Installing RISC-V tests'
module_all riscv-tests --prefix="${RISCV}/riscv${XLEN}-unknown-elf" --with-xlen=${XLEN}
@@ -115,6 +115,7 @@ echo '==> Installing DRAMSim2 Shared Library'
cd $RDIR
git submodule update --init tools/DRAMSim2
cd tools/DRAMSim2
make clean
make libdramsim.so
cp libdramsim.so $RISCV/lib/

1
scripts/init-submodules-no-riscv-tools-nolog.sh
View File

@@ -82,6 +82,7 @@ cd "$RDIR"
software/spec2017 \
tools/dsptools \
tools/rocket-dsp-utils \
tools/circt \
vlsi/hammer-mentor-plugins
do
"$1" "${name%/}"

4
scripts/insert-includes.py
View File

@@ -34,13 +34,15 @@ def process(inF, outF):
# for each include found, search through all dirs and replace if found, error if not
for num, line in enumerate(inFile, 1):
match = re.match(r"^ *`include +\"(.*)\"", line)
if match:
if match and match.group(1) != "uvm_macros.svh":
print("[INFO] Replacing includes for {}".format(match.group(1)))
# search for include and replace
found = False
for d in incDirs:
potentialIncFileName = d + "/" + match.group(1)
if os.path.exists(potentialIncFileName):
found = True
print("[INFO] Found missing include in {}".format(potentialIncFileName))
with open(potentialIncFileName, 'r') as incFile:
for iline in incFile:
outFile.write(iline)

4
scripts/uniquify-module-names.py
View File

@@ -110,7 +110,7 @@ def generate_copy(c, sfx):
new_file = os.path.join(args.gcpath, new_file)
shutil.copy(cur_file, new_file)
bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
bash(rf"{SED} -i 's/module\( \+\){cur_name}/module\1{new_name}/' {new_file}")
return new_file
def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
@@ -137,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
new_file = generate_copy(cur_file, MODEL_SFX)
if parent is not None and ((parent, mod) not in updated_submodule):
parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
bash(rf"{SED} -i 's/\( \*\){mod}\( \+\)/\1{mod}_{MODEL_SFX}\2/' {parent_file}")
updated_submodule.add((parent, mod))
# add the uniquified module to the verilog_modul_filename dict

2
sims/firesim

Submodule sims/firesim updated: 535dcdc29a...ac8bcd8b34

7
sims/vcs/vcs.mk
View File

@@ -50,14 +50,13 @@ VCS_NONCC_OPTS = \
+incdir+$(base_dir)/generators/radiance/src/main/resources/vsrc/vortex/third_party/fpnew/src/common_cells/include \
$(base_dir)/generators/radiance/src/main/resources/vsrc/vortex/third_party/fpnew/src/fpnew_pkg.sv \
$(base_dir)/generators/radiance/src/main/resources/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
$(base_dir)/generators/radiance/src/main/resources/vsrc/vortex/third_party/fpnew/src/common_cells/src/cb_filter_pkg.sv \
$(base_dir)/generators/radiance/src/main/resources/vsrc/vortex/third_party/fpnew/src/common_cells/src/cf_math_pkg.sv \
$(base_dir)/generators/radiance/src/main/resources/vsrc/vortex/third_party/fpnew/src/common_cells/src/ecc_pkg.sv \
-f $(sim_common_files) \
-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-debug_pp \
+incdir+$(GEN_COLLATERAL_DIR)
-top $(TB) \
+incdir+$(GEN_COLLATERAL_DIR) \
$(addprefix +incdir+,$(EXT_INCDIRS))
VCS_PREPROC_DEFINES = \
+define+VCS

1
sims/verilator/Makefile
View File

@@ -155,6 +155,7 @@ VERILATOR_NONCC_OPTS = \
-I$(GEN_COLLATERAL_DIR) \
--top-module $(TB) \
--vpi \
$(addprefix +incdir+,$(EXT_INCDIRS)) \
-f $(sim_common_files)
#----------------------------------------------------------------------------------------

2
software/firemarshal

Submodule software/firemarshal updated: b014183ac6...a98f1faff6

1
tests/hello.c
View File

@@ -1,6 +1,7 @@
#include <stdio.h>
#include <riscv-pk/encoding.h>
#include "marchid.h"
#include <stdint.h>
int main(void) {
uint64_t marchid = read_csr(marchid);

10
tests/symmetric.c
View File

@@ -1,5 +1,6 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <riscv-pk/encoding.h>
#include "marchid.h"
@@ -20,10 +21,13 @@ int main(void) {
memcpy(test, dest + OBUS_OFFSET, sizeof(src));
size_t read_end = rdcycle();
if (memcmp(src, test, sizeof(src))) {
printf("Remote write/read failed\n");
exit(1);
for (int i = 0; i < sizeof(src); i++) {
if (src[i] != test[i]) {
printf("Remote write/read failed at %p %p %p %x %x\n", src+i, test+i, dest + OBUS_OFFSET + i, src[i], test[i]);
exit(1);
}
}
printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start);
return 0;

2
toolchains/libgloss

Submodule toolchains/libgloss updated: 0ecdf7fa08...39234a1624

2
toolchains/riscv-tools/riscv-spike-devices

Submodule toolchains/riscv-tools/riscv-spike-devices updated: 8b4836db0b...39a0993b20

2
toolchains/riscv-tools/riscv-tools-feedstock

Submodule toolchains/riscv-tools/riscv-tools-feedstock updated: 917b56ef1a...56c29e01ba

1
tools/circt Submodule

Submodule tools/circt added at 9e0c1696f3

2
tools/rocket-dsp-utils

Submodule tools/rocket-dsp-utils updated: 272cee3c83...24bf9a27a8

8
variables.mk
View File

@@ -27,6 +27,7 @@ HELP_SIMULATION_VARIABLES = \
" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \
" BINARIES = list of riscv elf binary that the simulator will run when using the run-binaries* targets" \
" BINARIES_DIR = directory of riscv elf binaries that the simulator will run when using the run-binaries* targets" \
" BINARY_ARGS = arguments to pass to each binary in run-binary targets (primarily meant for pk arguments)" \
" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
@@ -224,6 +225,12 @@ BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f
# all module files to include (top, model, bb included)
ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f
# external filelists. Users, or project-supplied make fragments can append filelists
# with absolute paths here
EXT_FILELISTS ?=
# external verilog incdirs. Users, or project-supplied make fragments can append to this
EXT_INCDIRS ?=
BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img bootrom.radiance.rv32.img
BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
@@ -291,6 +298,7 @@ PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
BINARY ?=
BINARIES ?=
BINARY_ARGS ?=
override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
VERBOSE_FLAGS ?= +verbose
# get_out_name is a function, 1st argument is the binary

5
vlsi/Makefile
View File

@@ -72,7 +72,7 @@ VLSI_RTL = $(build_dir)/syn.f
ifneq ($(CUSTOM_VLOG), )
RTL_DEPS = $(CUSTOM_VLOG)
else
RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE)
RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) $(EXT_FILELISTS)
endif
$(VLSI_RTL): $(RTL_DEPS)
@@ -82,6 +82,9 @@ ifneq ($(CUSTOM_VLOG), )
else
cat $(TOP_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
ifneq ($(EXT_FILELISTS),)
cat $(EXT_FILELISTS) >> $(VLSI_RTL)
endif
endif
#########################################################################################

30
vlsi/make_syn_f.sh Executable file
View File

@@ -0,0 +1,30 @@
#!/bin/bash
# Check if an argument is provided
if [ "$#" -ne 1 ]; then
echo "Usage: $0 <directory_path>"
exit 1
fi
directory_path=$1
gen_collateral_path="${directory_path}/gen-collateral"
output_file="${directory_path}/syn.f"
if [ ! -d "$gen_collateral_path" ]; then
echo "The subdirectory gen-collateral does not exist in the provided directory."
exit 1
fi
# find "$gen_collateral_path" -type f \( -name "*.v" -o -name "*.sv" \) -exec realpath {} \; > "$output_file"
cat "${directory_path}/"*.top.f > "$output_file"
cat "${directory_path}/"*.bb.f | grep -E ".*v$" >> "$output_file"
find "$gen_collateral_path" -type f \( -name "*.top.mems.v" \) -exec realpath {} \; >> "$output_file"
temp_file=$(mktemp)
grep "pkg" "$output_file" > "$temp_file"
grep "defs_div" "$output_file" >> "$temp_file"
cat "$output_file" | grep -v "pkg" | grep -v "defs_div" | grep -E -v "Sim.*.v" | sort -u >> "$temp_file"
mv "$temp_file" "$output_file"
echo "File paths have been written to $output_file."