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Don't punch out uart2tsi debug io

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This commit is contained in:
Jerry Zhao
2023-12-26 09:39:08 -08:00
parent 902d33ebd1
commit 77c3b65fc9
1 changed files with 4 additions and 4 deletions
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8
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -25,11 +25,11 @@ import testchipip._
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi")
harnessIO <> port.io
val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
harnessIO <> port.io.uart
val packagePinsWithPackageIOs = Seq(
("A9" , IOPin(harnessIO.uart.rxd)),
("D10", IOPin(harnessIO.uart.txd)))
("A9" , IOPin(harnessIO.rxd)),
("D10", IOPin(harnessIO.txd)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")