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[vlsi][ci skip] Fix INPUT_CONFS override in tutorial.mk

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This commit is contained in:
Jerry Zhao
2023-10-19 11:19:56 -07:00
committed by GitHub
parent adc0f0ed0f
commit 77ee5906e2
1 changed files with 3 additions and 1 deletions
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4
vlsi/tutorial.mk
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@@ -12,6 +12,7 @@ ifeq ($(tutorial),asap7)
TECH_CONF ?= example-asap7.yml
DESIGN_CONFS ?=
VLSI_OBJ_DIR ?= build-asap7-commercial
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
endif
ifeq ($(tutorial),sky130-commercial)
@@ -23,6 +24,7 @@ ifeq ($(tutorial),sky130-commercial)
$(if $(filter $(VLSI_TOP),Rocket), \
example-designs/sky130-rocket.yml, )
VLSI_OBJ_DIR ?= build-sky130-commercial
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
endif
ifeq ($(tutorial),sky130-openroad)
@@ -36,8 +38,8 @@ ifeq ($(tutorial),sky130-openroad)
$(if $(filter $(VLSI_TOP),RocketTile), \
example-designs/sky130-openroad-rockettile.yml, )
VLSI_OBJ_DIR ?= build-sky130-openroad
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_YOSYS_FLOW = 1
endif
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)