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@@ -4,7 +4,7 @@ Adding a custom core
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====================
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You may want to add a custom RISC-V core to Chipyard generator. If the top module of your core is not in Chisel,
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you will first need to create a Verilog blackbox for it. See ::ref:`_incorporating-verilog-blocks` for instructions.
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you will first need to create a Verilog blackbox for it. See :ref:`incorporating-verilog-blocks` for instructions.
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Once you have a top module in Chisel, you are ready to create integrate it with Chipyard.
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.. note::
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@@ -184,7 +184,7 @@ in the tile class. Below is an example of how to connect a core using AXI4 to th
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:= AXI4Fragmenter() // deal with multi-beat xacts
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:= memAXI4Node) // The custom node, see below
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Remember, you may not need all of these intermediate widgets. See :::ref:`Diplomatic-Widgets` for the meaning of each intermediate
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Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate
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widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Also, Chipyard
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support AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol. See the reference page for
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more info.
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@@ -200,7 +200,7 @@ more info.
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id = IdRange(0, 1 << idBits))))))
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where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile.
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Make sure to read :::ref:`node-tyoes` to check out what type of nodes Chipyard supports and their parameters!
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Make sure to read :ref:`node_types` to check out what type of nodes Chipyard supports and their parameters!
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Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you
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can override the following two functions to control how to buffer the bus requests/responses:
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@@ -210,7 +210,7 @@ can override the following two functions to control how to buffer the bus reques
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protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer
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protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer
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You can find more information on ``TLBuffer`` in :::ref:`Diplomatic-Widgets`.
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You can find more information on ``TLBuffer`` in :ref:`diplomatic_widgets`.
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Interrupt
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---------
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@@ -313,20 +313,14 @@ the current config. An example of such config will be like this:
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.. code-block:: scala
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class WithNMyCores(n: Int) extends Config(
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new RegisterCore(new CoreEntry[MyTileParams, MyTile]("MyCore", MyTilesKey, MyCrossingKey)) ++
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new Config((site, here, up) => {
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case MyTilesKey => {
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List.tabulate(n)(i => MyTileParams(hartId = i))
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}
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})
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)
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Where ``RegisterCore`` will register the core with chipyard so that it can be recognized by generic config. This is required for
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all custom cores. You can also create other config fragments to change other parameters.
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class WithNMyCores(n: Int) extends Config((site, here, up) => {
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case MyTilesKey => {
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List.tabulate(n)(i => MyTileParams(hartId = i))
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}
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})
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Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions
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in :::ref:`_custom_chisel` to add your project to the build system, then create a config by following the steps in :::ref:`_hetero_socs_`.
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in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`.
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You can now run any desired workflow for the new config just as you do for the built-in cores.
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Appendix: Common Config Keys
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Zitao Fang