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Add cfg fragment to insert LLC interior buffers

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This commit is contained in:
Jerry Zhao
2023-11-16 02:59:26 -08:00
committed by GitHub
parent 846c8563fc
commit 7c832415a8
1 changed files with 8 additions and 1 deletions
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9
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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@@ -1,8 +1,9 @@
package chipyard.config
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper, InclusiveCacheKey}
import freechips.rocketchip.diplomacy.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
// Replaces the L2 with a broadcast manager for maintaining coherence
class WithBroadcastManager extends Config((site, here, up) => {
@@ -16,3 +17,9 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
case DTSTimebase => freqMHz
})
// Adds buffers on the interior of the inclusive L2, to improve PD
class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
})