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Use EICG_wrapper model as addResource/Path | Fix Makefile parsing

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abejgonzalez
2023-02-15 14:19:55 -08:00
parent 660c63fb34
commit 85fe061244
4 changed files with 2 additions and 8 deletions
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generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -51,6 +51,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)