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bump boom/firrtl | support building boom | update genfiles in simulator to make rv32 bootrom | misc cleanup

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This commit is contained in:
abejgonzalez
2019-04-17 17:08:08 -07:00
parent 80cbdd1d31
commit 885c5f74db
5 changed files with 5 additions and 4 deletions
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2
generators/boom

Submodule generators/boom updated: f1caea81c6...4cd347ed51

2
sims/verisim/Makefile
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@@ -89,5 +89,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
# general cleanup rule # general cleanup rule
######################################################################################### #########################################################################################
.PHONY: clean .PHONY: clean
clean: clean-scala clean:
rm -rf $(build_dir) $(sim_prefix)-* rm -rf $(build_dir) $(sim_prefix)-*

2
sims/vsim/Makefile
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@@ -93,5 +93,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
# general cleanup rule # general cleanup rule
######################################################################################### #########################################################################################
.PHONY: clean .PHONY: clean
clean: clean-scala clean:
rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h

1
src/main/scala/example/Simulator.scala
View File

@@ -101,6 +101,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
def writeBootrom(): Unit = { def writeBootrom(): Unit = {
firrtl.FileUtils.makeDirectory("./bootrom/") firrtl.FileUtils.makeDirectory("./bootrom/")
writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
} }
def writeFiles(cfg: GenerateSimConfig): Unit = { def writeFiles(cfg: GenerateSimConfig): Unit = {

2
tools/firrtl

Submodule tools/firrtl updated: 2272044c6a...bf66997b1a