first pass at xcelium support
This commit is contained in:
Sagar Karandikar
Submodule generators/testchipip updated: 6e8a684242...2d78a04538
@@ -111,4 +111,10 @@ if [ $TOOLCHAIN == "riscv-tools" ]; then
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make -C $RDIR/generators/gemmini/software/libgemmini install
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fi
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echo '==> Installing DRAMSim2 Shared Library'
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cd $RDIR
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cd tools/DRAMSim2
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make libdramsim.so
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cp libdramsim.so $RISCV/lib/
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echo "Extra Toolchain Utilities/Tests Build Complete!"
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141
sims/xcelium/Makefile
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141
sims/xcelium/Makefile
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@@ -0,0 +1,141 @@
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#########################################################################################
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# xcelium makefile
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#########################################################################################
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define CAD_INFO_HEADER
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# --------------------------------------------------------------------------------
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# This script was written and developed by Chipyard at UC Berkeley; however, the
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# underlying commands and reports are copyrighted by Cadence. We thank Cadence for
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# granting permission to share our research to help promote and foster the next
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# generation of innovators.
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# --------------------------------------------------------------------------------
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endef
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export CAD_INFO_HEADER
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#########################################################################################
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# general path variables
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#########################################################################################
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base_dir=$(abspath ../..)
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sim_dir=$(abspath .)
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#########################################################################################
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# include shared variables
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#########################################################################################
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include $(base_dir)/variables.mk
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#########################################################################################
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# name of simulator (used to generate *.f arguments file)
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#########################################################################################
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sim_name = xrun
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#########################################################################################
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# vcs simulator types and rules
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#########################################################################################
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sim_prefix = simx
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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sim_debug = $(sim)-debug
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sim_workdir = $(sim).xcelium.d
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sim_run_tcl = $(sim)_run.tcl
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sim_debug_run_tcl = $(sim_debug)_run.tcl
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include $(base_dir)/xcelium.mk
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.PHONY: default debug
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default: $(sim)
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debug: $(sim_debug)
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#########################################################################################
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# simulation requirements
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#########################################################################################
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SIM_FILE_REQS += \
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$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
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# copy files but ignore *.h files in *.f since xcelium has -Wcxx include
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$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
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cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
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$(foreach file,\
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$(SIM_FILE_REQS),\
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$(if $(filter %.h,$(file)),\
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,\
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echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
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#########################################################################################
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# import other necessary rules and variables
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#########################################################################################
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include $(base_dir)/common.mk
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#########################################################################################
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# vcs binary and arguments
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#########################################################################################
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VCS = xrun -64bit -elaborate
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#vcs -full64
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VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
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#########################################################################################
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# vcs build paths
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#########################################################################################
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model_dir = $(build_dir)/$(long_name)
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model_dir_debug = $(build_dir)/$(long_name).debug
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#########################################################################################
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# vcs simulator rules
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#########################################################################################
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$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
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rm -rf $(model_dir)
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$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -xmlibdirname $@
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$(sim_run_tcl): $(sim_workdir)
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echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
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echo "run" >> $(sim_run_tcl)
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echo "exit" >> $(sim_run_tcl)
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$(sim): $(sim_workdir) $(sim_run_tcl)
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echo "#!/usr/bin/env bash" > $(sim)
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echo "$$CAD_INFO_HEADER" >> $(sim)
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echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_run_tcl)" >> $(sim)
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chmod +x $(sim)
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$(sim_debug_run_tcl): $(sim_workdir)
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echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
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echo "database -open default_vcd_dump -vcd -into $(sim_out_name).vcd" >> $(sim_debug_run_tcl)
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echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
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echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
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echo "run" >> $(sim_debug_run_tcl)
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echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
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echo "exit" >> $(sim_debug_run_tcl)
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$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
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echo "#!/usr/bin/env bash" > $(sim_debug)
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echo "$$CAD_INFO_HEADER" >> $(sim_debug)
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echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 xrun +verbose +binary=super-awesome-program +permissive -R -xmlibdirname $(sim_workdir) -input $(sim_debug_run_tcl)" >> $(sim_debug)
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chmod +x $(sim_debug)
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#########################################################################################
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# create vcs vpd/fsdb rules
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#########################################################################################
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.PRECIOUS: $(output_dir)/%.vpd %.vpd
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$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
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.PRECIOUS: $(output_dir)/%.fsdb %.fsdb
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$(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +fsdbfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
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#########################################################################################
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# general cleanup rules
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#########################################################################################
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.PHONY: clean clean-sim clean-sim-debug
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clean:
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rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
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clean-sim:
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rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key
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clean-sim-debug:
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rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key
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Submodule toolchains/riscv-tools/riscv-isa-sim updated: e7d6aff19a...cd0a5dc550
77
xcelium.mk
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77
xcelium.mk
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@@ -0,0 +1,77 @@
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HELP_COMPILATION_VARIABLES += \
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" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB."
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HELP_SIMULATION_VARIABLES += \
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" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB."
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ifndef USE_VPD
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WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
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else
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WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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endif
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# If ntb_random_seed unspecified, vcs uses 1 as constant seed.
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# Set ntb_random_seed_automatic to actually get a random seed
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ifdef RANDOM_SEED
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SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
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else
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SEED_FLAG=+ntb_random_seed_automatic
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endif
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CLOCK_PERIOD ?= 1.0
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RESET_DELAY ?= 777.7
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#----------------------------------------------------------------------------------------
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# gcc configuration/optimization
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#----------------------------------------------------------------------------------------
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include $(base_dir)/sims/common-sim-flags.mk
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XC_CXX_PREFIX=-Wcxx,
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XC_LD_PREFIX=-Wld,
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REMOVE_RPATH=-Wl,-rpath%
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VCS_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS))
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VCS_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS)))
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# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate)
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VCS_CC_OPTS = \
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$(VCS_CXXFLAGS) \
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$(VCS_LDFLAGS) \
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-enable_rpath
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#-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \
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# $(filter -l%,$(VCS_LDFLAGS))
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VCS_NONCC_OPTS = \
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-fast_recompilation \
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-top $(TB) \
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-sv \
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-ALLOWREDEFINITION \
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-timescale 1ns/10ps \
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-define INTCNOPWR \
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-define INTC_NO_PWR_PINS \
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-define INTC_EMULATION \
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-f $(sim_common_files) \
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-logfile xrun_elab.log \
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-glsperf \
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-genafile access.txt \
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-notimingchecks \
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-delay_mode zero
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PREPROC_DEFINES = \
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-define VCS \
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-define CLOCK_PERIOD=$(CLOCK_PERIOD) \
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-define RESET_DELAY=$(RESET_DELAY) \
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-define PRINTF_COND=$(TB).printf_cond \
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-define STOP_COND=!$(TB).reset \
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-define MODEL=$(MODEL) \
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-define RANDOMIZE_MEM_INIT \
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-define RANDOMIZE_REG_INIT \
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-define RANDOMIZE_GARBAGE_ASSIGN \
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-define RANDOMIZE_INVALID_ASSIGN
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ifndef USE_VPD
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PREPROC_DEFINES += +define+FSDB
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endif
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