wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue.

Browse Source
This commit is contained in:
James Dunn
2020-10-11 11:12:33 -07:00
parent dca56cd858
commit 895dcd6831
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/src/main/scala/arty/HarnessBinders.scala
View File

@@ -30,7 +30,7 @@ import scala.reflect.{ClassTag}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => {
// (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
// ports.map { // ports.map {
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
} }
}) })
class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// UARTAdapter.connect(ports)(system.p) // UARTAdapter.connect(ports)(system.p)
@@ -70,4 +70,4 @@ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
// IOBUF(th.ck_io(3), ports.rxd) // IOBUF(th.ck_io(3), ports.rxd)
Nil Nil
} }
}) })