Merge remote-tracking branch 'origin/main' into tetheredsim
This commit is contained in:
Jerry Zhao
6
.github/scripts/defaults.sh
vendored
6
.github/scripts/defaults.sh
vendored
@@ -33,7 +33,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spif
|
||||
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
|
||||
grouping["group-constellation"]="chipyard-constellation"
|
||||
grouping["group-tracegen"]="tracegen tracegen-boom"
|
||||
grouping["group-other"]="icenet testchipip constellation"
|
||||
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
|
||||
grouping["group-fpga"]="arty vcu118 vc707"
|
||||
|
||||
# key value store to get the build strings
|
||||
@@ -70,6 +70,10 @@ mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
|
||||
mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
|
||||
mapping["icenet"]="SUB_PROJECT=icenet"
|
||||
mapping["testchipip"]="SUB_PROJECT=testchipip"
|
||||
mapping["rocketchip-amba"]="SUB_PROJECT=rocketchip CONFIG=AMBAUnitTestConfig"
|
||||
mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestConfig"
|
||||
mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
|
||||
mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"
|
||||
|
||||
mapping["arty"]="SUB_PROJECT=arty verilog"
|
||||
mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
|
||||
|
||||
12
.github/scripts/run-tests.sh
vendored
12
.github/scripts/run-tests.sh
vendored
@@ -139,6 +139,18 @@ case $1 in
|
||||
constellation)
|
||||
run_binary BINARY=none
|
||||
;;
|
||||
rocketchip-amba)
|
||||
run_binary BINARY=none
|
||||
;;
|
||||
rocketchip-tlsimple)
|
||||
run_binary BINARY=none
|
||||
;;
|
||||
rocketchip-tlwidth)
|
||||
run_binary BINARY=none
|
||||
;;
|
||||
rocketchip-tlxbar)
|
||||
run_binary BINARY=none
|
||||
;;
|
||||
*)
|
||||
echo "No set of tests for $1. Did you spell it right?"
|
||||
exit 1
|
||||
|
||||
6
.github/workflows/chipyard-full-flow.yml
vendored
6
.github/workflows/chipyard-full-flow.yml
vendored
@@ -80,7 +80,7 @@ jobs:
|
||||
eval "$(conda shell.bash hook)"
|
||||
mkdir ${{ env.JAVA_TMP_DIR }}
|
||||
export MAKEFLAGS="-j32"
|
||||
./build-setup.sh -f
|
||||
./build-setup.sh -f -v
|
||||
|
||||
run-cfg-finder:
|
||||
name: run-cfg-finder
|
||||
@@ -115,7 +115,7 @@ jobs:
|
||||
|
||||
cd vlsi
|
||||
|
||||
# NOTE: most conda installs are in separate conda envs because they mess up
|
||||
# NOTE: most conda installs are in separate conda envs because they mess up
|
||||
# each other's versions (for no apparent reason) and we need the latest versions
|
||||
conda config --add channels defaults
|
||||
conda config --add channels litex-hub
|
||||
@@ -166,7 +166,7 @@ jobs:
|
||||
name: cleanup
|
||||
needs: [run-tutorial]
|
||||
runs-on: ferry
|
||||
if: ${{ always() && contains(join(needs.*.result, ','), 'success') }}
|
||||
if: ${{ always() }}
|
||||
steps:
|
||||
- name: Delete repo copy and conda env
|
||||
run: |
|
||||
|
||||
40
.github/workflows/chipyard-run-tests.yml
vendored
40
.github/workflows/chipyard-run-tests.yml
vendored
@@ -880,6 +880,45 @@ jobs:
|
||||
group-key: "group-other"
|
||||
project-key: "testchipip"
|
||||
|
||||
rocketchip-run-tests:
|
||||
name: rocketchip-run-tests
|
||||
needs: prepare-chipyard-other
|
||||
runs-on: self-hosted
|
||||
steps:
|
||||
- name: Delete old checkout
|
||||
run: |
|
||||
ls -alh .
|
||||
rm -rf ${{ github.workspace }}/* || true
|
||||
rm -rf ${{ github.workspace }}/.* || true
|
||||
ls -alh .
|
||||
- name: Checkout
|
||||
uses: actions/checkout@v3
|
||||
- name: Git workaround
|
||||
uses: ./.github/actions/git-workaround
|
||||
- name: Create conda env
|
||||
uses: ./.github/actions/create-conda-env
|
||||
- name: Run amba tests
|
||||
uses: ./.github/actions/run-tests
|
||||
with:
|
||||
group-key: "group-other"
|
||||
project-key: "rocketchip-amba"
|
||||
# Below tests segfault with verilator, work fine in VCS
|
||||
# - name: Run tlsimple tests
|
||||
# uses: ./.github/actions/run-tests
|
||||
# with:
|
||||
# group-key: "group-other"
|
||||
# project-key: "rocketchip-tlsimple"
|
||||
# - name: Run tlwidth tests
|
||||
# uses: ./.github/actions/run-tests
|
||||
# with:
|
||||
# group-key: "group-other"
|
||||
# project-key: "rocketchip-tlwidth"
|
||||
# - name: Run tlxbar tests
|
||||
# uses: ./.github/actions/run-tests
|
||||
# with:
|
||||
# group-key: "group-other"
|
||||
# project-key: "rocketchip-tlxbar"
|
||||
|
||||
constellation-run-tests:
|
||||
name: constellation-run-tests
|
||||
needs: prepare-chipyard-other
|
||||
@@ -1004,6 +1043,7 @@ jobs:
|
||||
tracegen-run-tests,
|
||||
icenet-run-tests,
|
||||
testchipip-run-tests,
|
||||
rocketchip-run-tests,
|
||||
constellation-run-tests,
|
||||
prepare-chipyard-fpga, # firesim-run-tests,
|
||||
fireboom-run-tests]
|
||||
|
||||
1
.gitignore
vendored
1
.gitignore
vendored
@@ -26,3 +26,4 @@ project/metals.sbt
|
||||
project/project/
|
||||
.ivy2
|
||||
.sbt
|
||||
.classpath_cache/
|
||||
|
||||
31
build.sbt
31
build.sbt
@@ -4,14 +4,34 @@ import Tests._
|
||||
// implicit one
|
||||
lazy val chipyardRoot = Project("chipyardRoot", file("."))
|
||||
|
||||
// keep chisel/firrtl specific class files, rename other conflicts
|
||||
val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
|
||||
import sbtassembly.Assembly.{Project, Library}
|
||||
val nm = dep match {
|
||||
case p: Project => p.name
|
||||
case l: Library => l.moduleCoord.name
|
||||
}
|
||||
if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
|
||||
dep.target
|
||||
} else {
|
||||
"renamed/" + dep.target
|
||||
}
|
||||
}
|
||||
|
||||
lazy val commonSettings = Seq(
|
||||
organization := "edu.berkeley.cs",
|
||||
version := "1.6",
|
||||
scalaVersion := "2.13.10",
|
||||
assembly / test := {},
|
||||
assembly / assemblyMergeStrategy := { _ match {
|
||||
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
|
||||
case _ => MergeStrategy.first}},
|
||||
assembly / assemblyMergeStrategy := {
|
||||
case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
|
||||
case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
|
||||
// should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
|
||||
case x if x.endsWith("module-info.class") => MergeStrategy.discard
|
||||
case x =>
|
||||
val oldStrategy = (assembly / assemblyMergeStrategy).value
|
||||
oldStrategy(x)
|
||||
},
|
||||
scalacOptions ++= Seq(
|
||||
"-deprecation",
|
||||
"-unchecked",
|
||||
@@ -86,8 +106,6 @@ lazy val hardfloat = (project in rocketChipDir / "hardfloat")
|
||||
.settings(commonSettings)
|
||||
.settings(
|
||||
libraryDependencies ++= Seq(
|
||||
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
|
||||
"org.json4s" %% "json4s-jackson" % "3.6.6",
|
||||
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
|
||||
)
|
||||
)
|
||||
@@ -97,8 +115,6 @@ lazy val rocketMacros = (project in rocketChipDir / "macros")
|
||||
.settings(
|
||||
libraryDependencies ++= Seq(
|
||||
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
|
||||
"org.json4s" %% "json4s-jackson" % "3.6.6",
|
||||
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
|
||||
)
|
||||
)
|
||||
|
||||
@@ -225,7 +241,6 @@ lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "sr
|
||||
lazy val tapeout = (project in file("./tools/barstools/"))
|
||||
.settings(chiselSettings)
|
||||
.settings(chiselTestSettings)
|
||||
.enablePlugins(sbtassembly.AssemblyPlugin)
|
||||
.settings(commonSettings)
|
||||
|
||||
lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
|
||||
|
||||
52
common.mk
52
common.mk
@@ -16,7 +16,6 @@ HELP_COMPILATION_VARIABLES += \
|
||||
" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \
|
||||
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
|
||||
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
|
||||
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
|
||||
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
|
||||
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
|
||||
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
|
||||
@@ -52,7 +51,6 @@ HELP_COMMANDS += \
|
||||
" firrtl = generate intermediate firrtl files from chisel elaboration" \
|
||||
" run-tests = run all assembly and benchmark tests" \
|
||||
" launch-sbt = start sbt terminal" \
|
||||
" {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \
|
||||
" find-config-fragments = list all config. fragments"
|
||||
|
||||
#########################################################################################
|
||||
@@ -105,12 +103,24 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
|
||||
cp -f $< $@
|
||||
|
||||
#########################################################################################
|
||||
# create firrtl file rule and variables
|
||||
# compile scala jars
|
||||
#########################################################################################
|
||||
$(CHIPYARD_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
|
||||
mkdir -p $(dir $@)
|
||||
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
|
||||
|
||||
# order only dependency between sbt runs needed to avoid concurrent sbt runs
|
||||
$(TAPEOUT_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS)
|
||||
mkdir -p $(dir $@)
|
||||
$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
|
||||
|
||||
#########################################################################################
|
||||
# verilog generation pipeline
|
||||
#########################################################################################
|
||||
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
|
||||
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
|
||||
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
|
||||
mkdir -p $(build_dir)
|
||||
(set -o pipefail && $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
|
||||
(set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
|
||||
--target-dir $(build_dir) \
|
||||
--name $(long_name) \
|
||||
--top-module $(MODEL_PACKAGE).$(MODEL) \
|
||||
@@ -195,9 +205,9 @@ endif
|
||||
if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
|
||||
|
||||
$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
|
||||
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
|
||||
$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
|
||||
rm -rf $(GEN_COLLATERAL_DIR)
|
||||
$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
|
||||
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
|
||||
--no-dedup \
|
||||
--output-file $(SFC_FIRRTL_BASENAME) \
|
||||
--output-annotation-file $(SFC_ANNO_FILE) \
|
||||
@@ -263,12 +273,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
|
||||
|
||||
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
|
||||
TOP_MACROCOMPILER_MODE ?= --mode synflops
|
||||
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
|
||||
$(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
|
||||
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
|
||||
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
|
||||
|
||||
MODEL_MACROCOMPILER_MODE = --mode synflops
|
||||
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
|
||||
$(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
|
||||
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
|
||||
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
|
||||
|
||||
########################################################################################
|
||||
# remove duplicate files and headers in list of simulation file inputs
|
||||
@@ -391,7 +401,6 @@ endif
|
||||
#######################################
|
||||
# Rules for building DRAMSim2 library
|
||||
#######################################
|
||||
|
||||
dramsim_dir = $(base_dir)/tools/DRAMSim2
|
||||
dramsim_lib = $(dramsim_dir)/libdramsim.a
|
||||
|
||||
@@ -399,27 +408,12 @@ $(dramsim_lib):
|
||||
$(MAKE) -C $(dramsim_dir) $(notdir $@)
|
||||
|
||||
################################################
|
||||
# Helper to run SBT or manage the SBT server
|
||||
# Helper to run SBT
|
||||
################################################
|
||||
|
||||
SBT_COMMAND ?= shell
|
||||
.PHONY: launch-sbt
|
||||
launch-sbt:
|
||||
cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)"
|
||||
|
||||
.PHONY: check-thin-client
|
||||
check-thin-client:
|
||||
ifeq (,$(ENABLE_SBT_THIN_CLIENT))
|
||||
$(error ENABLE_SBT_THIN_CLIENT not set.)
|
||||
endif
|
||||
|
||||
.PHONY: shutdown-sbt-server
|
||||
shutdown-sbt-server: check-thin-client
|
||||
cd $(base_dir) && $(SBT) "shutdown"
|
||||
|
||||
.PHONY: start-sbt-server
|
||||
start-sbt-server: check-thin-client
|
||||
cd $(base_dir) && $(SBT) "exit"
|
||||
cd $(base_dir) && $(SBT) "$(SBT_COMMAND)"
|
||||
|
||||
#########################################################################################
|
||||
# print help text (and other help)
|
||||
|
||||
@@ -93,7 +93,7 @@ dependencies:
|
||||
- screen
|
||||
- elfutils
|
||||
- libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
|
||||
- conda-lock>=1
|
||||
- conda-lock=1
|
||||
|
||||
# clang-format for driver coding style enforcement.
|
||||
- clang-format
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -46,7 +46,7 @@ This is done by the following:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
conda install -n base conda-lock
|
||||
conda install -n base conda-lock=1
|
||||
conda activate base
|
||||
|
||||
.. Note:: We also recommended switching to `libmamba <https://www.anaconda.com/blog/a-faster-conda-for-a-growing-community>`__ for much faster dependency solving.
|
||||
|
||||
Submodule fpga/fpga-shells updated: 9f4c6ac571...d650f81c07
@@ -84,7 +84,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
|
||||
name = "chip_ddr",
|
||||
sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
|
||||
)))))
|
||||
ddrNode := ddrClient
|
||||
ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
|
||||
|
||||
// module implementation
|
||||
override lazy val module = new VCU118FPGATestHarnessImp(this)
|
||||
|
||||
Submodule generators/boom updated: 679f358755...f732ceb602
@@ -72,17 +72,18 @@ object SpikeCosim
|
||||
})
|
||||
cosim.io.hartid := hartid.U
|
||||
for (i <- 0 until trace.numInsns) {
|
||||
cosim.io.trace(i).valid := trace.insns(i).valid
|
||||
val insn = trace.trace.insns(i)
|
||||
cosim.io.trace(i).valid := insn.valid
|
||||
val signed = Wire(SInt(64.W))
|
||||
signed := trace.insns(i).iaddr.asSInt
|
||||
signed := insn.iaddr.asSInt
|
||||
cosim.io.trace(i).iaddr := signed.asUInt
|
||||
cosim.io.trace(i).insn := trace.insns(i).insn
|
||||
cosim.io.trace(i).exception := trace.insns(i).exception
|
||||
cosim.io.trace(i).interrupt := trace.insns(i).interrupt
|
||||
cosim.io.trace(i).cause := trace.insns(i).cause
|
||||
cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B
|
||||
cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U)
|
||||
cosim.io.trace(i).priv := trace.insns(i).priv
|
||||
cosim.io.trace(i).insn := insn.insn
|
||||
cosim.io.trace(i).exception := insn.exception
|
||||
cosim.io.trace(i).interrupt := insn.interrupt
|
||||
cosim.io.trace(i).cause := insn.cause
|
||||
cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B
|
||||
cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U)
|
||||
cosim.io.trace(i).priv := insn.priv
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -62,6 +62,7 @@ case class SpikeCoreParams() extends CoreParams {
|
||||
val useBitManipCrypto = false
|
||||
val useCryptoNIST = false
|
||||
val useCryptoSM = false
|
||||
val useConditionalZero = false
|
||||
|
||||
override def vLen = 128
|
||||
override def vMemDataBits = 128
|
||||
|
||||
@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
|
||||
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
|
||||
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
|
||||
|
||||
tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
|
||||
tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
|
||||
tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
|
||||
clockDivider.tlNode := system.prci_ctrl_bus
|
||||
clockSelector.tlNode := system.prci_ctrl_bus
|
||||
pllCtrl.tlNode := system.prci_ctrl_bus
|
||||
|
||||
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
|
||||
|
||||
|
||||
@@ -23,9 +23,9 @@ object ClockGroupCombiner {
|
||||
case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil)
|
||||
|
||||
// All clock groups with a name containing any substring in names will be combined into a single clock group
|
||||
class WithClockGroupsCombinedByName(groups: (String, Seq[String])*) extends Config((site, here, up) => {
|
||||
case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names) =>
|
||||
(grouped_name, (m: ClockSinkParameters) => matched_names.map(n => m.name.get.contains(n)).reduce(_||_))
|
||||
class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => {
|
||||
case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) =>
|
||||
(grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n)))
|
||||
}
|
||||
})
|
||||
|
||||
|
||||
@@ -36,6 +36,14 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
|
||||
val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
|
||||
prci_ctrl_domain.clockNode := tlbus.fixedClockNode
|
||||
|
||||
val prci_ctrl_bus = prci_ctrl_domain { TLXbar() }
|
||||
tlbus.coupleTo("prci_ctrl") { (prci_ctrl_bus
|
||||
:= TLFIFOFixer(TLFIFOFixer.all)
|
||||
:= TLFragmenter(tlbus.beatBytes, tlbus.blockBytes)
|
||||
:= TLBuffer()
|
||||
:= _)
|
||||
}
|
||||
|
||||
// Aggregate all the clock groups into a single node
|
||||
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
|
||||
val allClockGroupsNode = ClockGroupEphemeralNode()
|
||||
@@ -71,19 +79,24 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
|
||||
// diplomatic IOBinder should drive
|
||||
val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
|
||||
val clockGroupCombiner = ClockGroupCombiner()
|
||||
val resetSynchronizer = ClockGroupResetSynchronizer()
|
||||
val tileClockGater = if (prciParams.enableTileClockGating) { prci_ctrl_domain {
|
||||
TileClockGater(prciParams.baseAddress + 0x00000, tlbus)
|
||||
} } else { ClockGroupEphemeralNode() }
|
||||
val tileResetSetter = if (prciParams.enableTileResetSetting) { prci_ctrl_domain {
|
||||
TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)
|
||||
} } else { ClockGroupEphemeralNode() }
|
||||
val resetSynchronizer = prci_ctrl_domain { ClockGroupResetSynchronizer() }
|
||||
val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
|
||||
val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
|
||||
clock_gater.tlNode := prci_ctrl_bus
|
||||
clock_gater
|
||||
} }
|
||||
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
|
||||
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
|
||||
tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
|
||||
reset_setter.tlNode := prci_ctrl_bus
|
||||
reset_setter
|
||||
} }
|
||||
|
||||
(aggregator
|
||||
:= frequencySpecifier
|
||||
:= clockGroupCombiner
|
||||
:= resetSynchronizer
|
||||
:= tileClockGater
|
||||
:= tileResetSetter
|
||||
:= tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
|
||||
:= tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
|
||||
:= allClockGroupsNode)
|
||||
}
|
||||
|
||||
@@ -26,20 +26,26 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
|
||||
val sinks = clockNode.out.head._1.member.elements.toSeq
|
||||
require (sources.size == sinks.size)
|
||||
val nSinks = sinks.size
|
||||
// The implicit clock of this module is the clock of the tilelink bus
|
||||
// busReset is sync'd to that clock, and will be asserted longer than the
|
||||
// resets coming in through the clockNode, since the busReset is derived from
|
||||
// the clockNode resets in downstream PRCI nodes
|
||||
val busReset = reset
|
||||
|
||||
val regs = (0 until nSinks) .map { i =>
|
||||
val sinkName = sinks(i)._1
|
||||
val asyncReset = sources(i).reset
|
||||
val reg = withReset (asyncReset) {
|
||||
Module(new AsyncResetRegVec(w=divBits, init=0))
|
||||
}
|
||||
val reg = Module(new AsyncResetRegVec(w=divBits, init=0))
|
||||
|
||||
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
|
||||
sinks(i)._2.clock := withClockAndReset(sources(i).clock, asyncReset) {
|
||||
val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
|
||||
divider.io.divisor := reg.io.q
|
||||
divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
|
||||
divider.io.clockOut
|
||||
}
|
||||
val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
|
||||
divider.io.clockIn := sources(i).clock
|
||||
// busReset is expected to be high for a long time, since reset will take a while to propagate
|
||||
// to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock
|
||||
// by setting divisor=0. The divisor signal into the ClockDividerOrPass is synchronized internally
|
||||
divider.io.divisor := Mux(busReset.asBool, 0.U, reg.io.q)
|
||||
divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
|
||||
sinks(i)._2.clock := divider.io.clockOut
|
||||
|
||||
// Note this is not synchronized to the output clock, which takes time to appear
|
||||
// so this is still asyncreset
|
||||
|
||||
@@ -46,10 +46,3 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
|
||||
}
|
||||
}
|
||||
|
||||
object TileClockGater {
|
||||
def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = {
|
||||
val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes))
|
||||
tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() }
|
||||
gater.clockNode
|
||||
}
|
||||
}
|
||||
|
||||
@@ -62,12 +62,3 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
object TileResetSetter {
|
||||
def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = {
|
||||
val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts))
|
||||
tlbus.toVariableWidthSlave(Some("tile-reset-setter")) { setter.tlNode := TLBuffer() }
|
||||
setter.clockNode
|
||||
}
|
||||
}
|
||||
|
||||
@@ -48,7 +48,7 @@ class AbstractConfig extends Config(
|
||||
|
||||
// By default, punch out IOs to the Harness
|
||||
new chipyard.clocking.WithPassthroughClockGenerator ++
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"))) ++
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
|
||||
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
|
||||
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
|
||||
|
||||
|
||||
@@ -40,7 +40,7 @@ class ChipLikeRocketConfig extends Config(
|
||||
new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure
|
||||
|
||||
// Create the uncore clock group
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"))) ++
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"), Nil)) ++
|
||||
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
|
||||
@@ -78,8 +78,8 @@ class MulticlockRocketConfig extends Config(
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
// Frequency specifications
|
||||
new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit")),
|
||||
("periphery", Seq("pbus", "fbus"))) ++
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil),
|
||||
("periphery", Seq("pbus", "fbus"), Nil)) ++
|
||||
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540
|
||||
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
|
||||
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
|
||||
|
||||
@@ -11,7 +11,7 @@ class AbstractTraceGenConfig extends Config(
|
||||
new chipyard.iobinders.WithAXI4MemPunchthrough ++
|
||||
new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
|
||||
new chipyard.clocking.WithPassthroughClockGenerator ++
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"))) ++
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
|
||||
new chipyard.config.WithTracegenSystem ++
|
||||
new chipyard.config.WithNoSubsystemDrivenClocks ++
|
||||
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
|
||||
|
||||
@@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.prci._
|
||||
import freechips.rocketchip.util._
|
||||
import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
|
||||
import freechips.rocketchip.tilelink.{TLBuffer}
|
||||
import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter}
|
||||
import chipyard.{BuildSystem, DigitalTop}
|
||||
import chipyard.clocking._
|
||||
import chipyard.iobinders.{IOCellKey, JTAGChipIO}
|
||||
@@ -33,9 +33,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
|
||||
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
|
||||
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
|
||||
|
||||
tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
|
||||
tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
|
||||
tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
|
||||
tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
|
||||
tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
|
||||
tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
|
||||
|
||||
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
|
||||
|
||||
|
||||
@@ -165,17 +165,17 @@ trait CanHavePeripheryGCD { this: BaseSubsystem =>
|
||||
case Some(params) => {
|
||||
if (params.useAXI4) {
|
||||
val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p))
|
||||
pbus.toSlave(Some(portName)) {
|
||||
pbus.coupleTo(portName) {
|
||||
gcd.node :=
|
||||
AXI4Buffer () :=
|
||||
TLToAXI4 () :=
|
||||
// toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx
|
||||
TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true)
|
||||
TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _
|
||||
}
|
||||
Some(gcd)
|
||||
} else {
|
||||
val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p))
|
||||
pbus.toVariableWidthSlave(Some(portName)) { gcd.node }
|
||||
pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
|
||||
Some(gcd)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -62,7 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
|
||||
|
||||
p(InitZeroKey) .map { k =>
|
||||
val initZero = LazyModule(new InitZero()(p))
|
||||
fbus.fromPort(Some("init-zero"))() := initZero.node
|
||||
fbus.coupleFrom("init-zero") { _ := initZero.node }
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -67,6 +67,7 @@ case class MyCoreParams(
|
||||
val useCryptoNIST: Boolean = false
|
||||
val useCryptoSM: Boolean = false
|
||||
val traceHasWdata: Boolean = false
|
||||
val useConditionalZero = false
|
||||
}
|
||||
|
||||
// DOC include start: CanAttachTile
|
||||
|
||||
@@ -203,7 +203,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
|
||||
genOut = FixedPoint(8.W, 3.BP),
|
||||
coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
|
||||
params = params))
|
||||
pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() }
|
||||
pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
|
||||
Some(streamingFIR)
|
||||
}
|
||||
case None => None
|
||||
|
||||
@@ -132,7 +132,7 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
|
||||
val passthrough = p(StreamingPassthroughKey) match {
|
||||
case Some(params) => {
|
||||
val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
|
||||
pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() }
|
||||
pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
|
||||
Some(streamingPassthroughChain)
|
||||
}
|
||||
case None => None
|
||||
|
||||
Submodule generators/cva6 updated: 0011494bb7...46323fcd74
Submodule generators/fft-generator updated: be8ab768bd...f598d0c359
@@ -38,16 +38,22 @@ class FireSimClockBridgeInstantiator extends HarnessClockInstantiator {
|
||||
|
||||
var instantiatedClocks = LinkedHashMap[Int, (Clock, Seq[String])]()
|
||||
// connect wires to clock source
|
||||
for ((name, (freq, clock)) <- clockMap) {
|
||||
val freqMHz = (freq / (1000 * 1000)).toInt
|
||||
def findOrInstantiate(freqMHz: Int, name: String): Clock = {
|
||||
if (!instantiatedClocks.contains(freqMHz)) {
|
||||
val clock = Wire(Clock())
|
||||
instantiatedClocks(freqMHz) = (clock, Seq(name))
|
||||
} else {
|
||||
instantiatedClocks(freqMHz) = (instantiatedClocks(freqMHz)._1, instantiatedClocks(freqMHz)._2 :+ name)
|
||||
}
|
||||
clock := instantiatedClocks(freqMHz)._1
|
||||
instantiatedClocks(freqMHz)._1
|
||||
}
|
||||
for ((name, (freq, clock)) <- clockMap) {
|
||||
val freqMHz = (freq / (1000 * 1000)).toInt
|
||||
clock := findOrInstantiate(freqMHz, name)
|
||||
}
|
||||
|
||||
// The undivided reference clock as calculated by pllConfig must be instantiated
|
||||
findOrInstantiate(pllConfig.referenceFreqMHz.toInt, "reference")
|
||||
|
||||
val ratClocks = instantiatedClocks.map { case (freqMHz, (clock, names)) =>
|
||||
(RationalClock(names.mkString(","), 1, pllConfig.referenceFreqMHz.toInt / freqMHz), clock)
|
||||
|
||||
@@ -103,11 +103,15 @@ class WithFireSimDesignTweaks extends Config(
|
||||
|
||||
// Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
|
||||
class WithFireSimHighPerfClocking extends Config(
|
||||
// Create clock group for uncore that does not include mbus
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Nil)) ++
|
||||
// Optional: This sets the default frequency for all buses in the system to 3.2 GHz
|
||||
// (since unspecified bus frequencies will use the pbus frequency)
|
||||
// This frequency selection matches FireSim's legacy selection and is required
|
||||
// to support 200Gb NIC performance. You may select a smaller value.
|
||||
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
|
||||
new chipyard.config.WithSystemBusFrequency(3200.0) ++
|
||||
new chipyard.config.WithFrontBusFrequency(3200.0) ++
|
||||
// Optional: These three configs put the DRAM memory system in it's own clock domain.
|
||||
// Removing the first config will result in the FASED timing model running
|
||||
// at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.
|
||||
@@ -164,6 +168,23 @@ class WithFireSimHighPerfConfigTweaks extends Config(
|
||||
new WithFireSimDesignTweaks
|
||||
)
|
||||
|
||||
// Tweak more representative of testchip configs
|
||||
class WithFireSimTestChipConfigTweaks extends Config(
|
||||
// Frequency specifications
|
||||
new chipyard.config.WithTileFrequency(1000.0) ++ // Realistic tile frequency for a test chip
|
||||
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency
|
||||
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately
|
||||
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
|
||||
// Crossing specifications
|
||||
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
|
||||
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
|
||||
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
|
||||
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
|
||||
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
|
||||
new WithFireSimDesignTweaks
|
||||
)
|
||||
|
||||
/*******************************************************************************
|
||||
* Full TARGET_CONFIG configurations. These set parameters of the target being
|
||||
* simulated.
|
||||
|
||||
Submodule generators/ibex updated: 916fb7a6ff...66ec6e56ed
Submodule generators/icenet updated: ce1ec55c1f...68b4c7f30f
Submodule generators/nvdla updated: 7130a5c0f7...730fad4360
Submodule generators/riscv-sodor updated: c051956d3b...c1c809ebd5
Submodule generators/rocket-chip updated: 25e2c63567...47f7b71447
Submodule generators/sha3 updated: 1fa5ef8ae5...b19b7c76fc
Submodule generators/testchipip updated: 456223c916...9040132618
@@ -1,3 +1,3 @@
|
||||
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
|
||||
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1")
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4")
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3")
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.6")
|
||||
|
||||
@@ -26,10 +26,13 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
|
||||
popd
|
||||
)
|
||||
(
|
||||
pushd $RDIR/generators/cva6/src/main/resources/vsrc
|
||||
if [ -d cva6 ]
|
||||
if [ -d $RDIR/generators/cva6/src/main/resources/cva6/vsrc ]
|
||||
then
|
||||
git submodule deinit -f cva6
|
||||
pushd $RDIR/generators/cva6/src/main/resources/cva6/vsrc
|
||||
if [ -d cva6 ]
|
||||
then
|
||||
git submodule deinit -f cva6
|
||||
fi
|
||||
popd
|
||||
fi
|
||||
popd
|
||||
)
|
||||
|
||||
Submodule sims/firesim updated: 966e09907c...b000772990
@@ -93,7 +93,7 @@ $(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
|
||||
#########################################################################################
|
||||
.PHONY: clean clean-sim clean-sim-debug
|
||||
clean:
|
||||
rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
|
||||
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-* ucli.key
|
||||
|
||||
clean-sim:
|
||||
rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key
|
||||
|
||||
@@ -226,7 +226,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
|
||||
#########################################################################################
|
||||
.PHONY: clean clean-sim clean-sim-debug
|
||||
clean:
|
||||
rm -rf $(gen_dir) $(sim_prefix)-*
|
||||
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
|
||||
|
||||
clean-sim:
|
||||
rm -rf $(model_dir) $(sim)
|
||||
|
||||
@@ -77,7 +77,6 @@ XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
|
||||
model_dir = $(build_dir)/$(long_name)
|
||||
model_dir_debug = $(build_dir)/$(long_name).debug
|
||||
|
||||
|
||||
#########################################################################################
|
||||
# xcelium simulator rules
|
||||
#########################################################################################
|
||||
@@ -87,37 +86,35 @@ $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
|
||||
$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
|
||||
|
||||
$(sim_run_tcl): $(sim_workdir)
|
||||
echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
|
||||
echo "run" >> $(sim_run_tcl)
|
||||
echo "exit" >> $(sim_run_tcl)
|
||||
echo "$$CAD_INFO_HEADER" > $@
|
||||
echo "run" >> $@
|
||||
echo "exit" >> $@
|
||||
|
||||
# The system libstdc++ may not link correctly with some of our dynamic libs, so
|
||||
# force loading the conda one (if present) with LD_PRELOAD
|
||||
$(sim): $(sim_workdir) $(sim_run_tcl)
|
||||
echo "#!/usr/bin/env bash" > $(sim)
|
||||
echo "$$CAD_INFO_HEADER" >> $(sim)
|
||||
cat arg-reshuffle >> $(sim)
|
||||
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
|
||||
chmod +x $(sim)
|
||||
echo "#!/usr/bin/env bash" > $@
|
||||
echo "$$CAD_INFO_HEADER" >> $@
|
||||
cat arg-reshuffle >> $@
|
||||
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
|
||||
chmod +x $@
|
||||
|
||||
$(sim_debug_run_tcl): $(sim_workdir)
|
||||
echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
|
||||
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
|
||||
echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
|
||||
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
|
||||
echo "run" >> $(sim_debug_run_tcl)
|
||||
echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
|
||||
echo "exit" >> $(sim_debug_run_tcl)
|
||||
|
||||
echo "$$CAD_INFO_HEADER" > $@
|
||||
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $@
|
||||
echo "set probe_packed_limit 64k" >> $@
|
||||
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $@
|
||||
echo "run" >> $@
|
||||
echo "database -close default_vcd_dump" >> $@
|
||||
echo "exit" >> $@
|
||||
|
||||
$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
|
||||
echo "#!/usr/bin/env bash" > $(sim_debug)
|
||||
echo "$$CAD_INFO_HEADER" >> $(sim_debug)
|
||||
cat arg-reshuffle >> $(sim_debug)
|
||||
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
|
||||
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
|
||||
chmod +x $(sim_debug)
|
||||
|
||||
echo "#!/usr/bin/env bash" > $@
|
||||
echo "$$CAD_INFO_HEADER" >> $@
|
||||
cat arg-reshuffle >> $@
|
||||
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $@
|
||||
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
|
||||
chmod +x $@
|
||||
|
||||
#########################################################################################
|
||||
# create vcd rules
|
||||
@@ -131,7 +128,7 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
|
||||
#########################################################################################
|
||||
.PHONY: clean clean-sim clean-sim-debug
|
||||
clean:
|
||||
rm -rf $(gen_dir) $(sim_prefix)-*
|
||||
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
|
||||
|
||||
clean-sim:
|
||||
rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
|
||||
|
||||
Submodule tools/barstools updated: 30900965f0...fe81afec14
57
variables.mk
57
variables.mk
@@ -8,7 +8,7 @@ HELP_COMPILATION_VARIABLES = \
|
||||
" JAVA_TOOL_OPTIONS = if overridden, set underlying java tool options (default sets misc. sizes and tmp dir)" \
|
||||
" SBT_OPTS = set additional sbt command line options (these take the form -Dsbt.<option>=<setting>) " \
|
||||
" See https://www.scala-sbt.org/1.x/docs/Command-Line-Reference.html\#Command+Line+Options" \
|
||||
" SBT_BIN = if overridden, used to invoke sbt (default is to invoke sbt by sbt-launch.jar)" \
|
||||
" SBT = if overridden, used to invoke sbt (default is to invoke sbt by sbt-launch.jar)" \
|
||||
" FIRRTL_LOGLEVEL = if overridden, set firrtl log level (default is error)"
|
||||
|
||||
HELP_PROJECT_VARIABLES = \
|
||||
@@ -90,7 +90,7 @@ ifeq ($(SUB_PROJECT),hwacha)
|
||||
TB ?= TestDriver
|
||||
TOP ?= ExampleRocketSystem
|
||||
endif
|
||||
# For TestChipIP developers
|
||||
# For TestChipIP developers running unit-tests
|
||||
ifeq ($(SUB_PROJECT),testchipip)
|
||||
SBT_PROJECT ?= chipyard
|
||||
MODEL ?= TestHarness
|
||||
@@ -102,6 +102,18 @@ ifeq ($(SUB_PROJECT),testchipip)
|
||||
TB ?= TestDriver
|
||||
TOP ?= UnitTestSuite
|
||||
endif
|
||||
# For rocketchip developers running unit-tests
|
||||
ifeq ($(SUB_PROJECT),rocketchip)
|
||||
SBT_PROJECT ?= chipyard
|
||||
MODEL ?= TestHarness
|
||||
VLOG_MODEL ?= $(MODEL)
|
||||
MODEL_PACKAGE ?= chipyard.unittest
|
||||
CONFIG ?= TLSimpleUnitTestConfig
|
||||
CONFIG_PACKAGE ?= freechips.rocketchip.unittest
|
||||
GENERATOR_PACKAGE ?= chipyard
|
||||
TB ?= TestDriver
|
||||
TOP ?= UnitTestSuite
|
||||
endif
|
||||
# For IceNet developers
|
||||
ifeq ($(SUB_PROJECT),icenet)
|
||||
SBT_PROJECT ?= chipyard
|
||||
@@ -146,6 +158,14 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
|
||||
long_name=$(MODEL_PACKAGE).$(CONFIG)
|
||||
endif
|
||||
|
||||
# classpaths
|
||||
CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache
|
||||
CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar
|
||||
TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar
|
||||
# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
|
||||
CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
|
||||
TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))
|
||||
|
||||
# chisel generated outputs
|
||||
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
|
||||
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
|
||||
@@ -206,32 +226,37 @@ sim_common_files ?= $(build_dir)/sim_files.common.f
|
||||
#########################################################################################
|
||||
JAVA_HEAP_SIZE ?= 8G
|
||||
JAVA_TMP_DIR ?= $(base_dir)/.java_tmp
|
||||
export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(JAVA_TMP_DIR)
|
||||
export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(JAVA_TMP_DIR)
|
||||
|
||||
#########################################################################################
|
||||
# default sbt launch command
|
||||
#########################################################################################
|
||||
SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)
|
||||
|
||||
SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
|
||||
|
||||
ifdef ENABLE_SBT_THIN_CLIENT
|
||||
SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
|
||||
# enabling speeds up sbt loading
|
||||
# use with sbt script or sbtn to bypass error code issues
|
||||
SBT_CLIENT_FLAG = --client
|
||||
endif
|
||||
|
||||
# passes $(JAVA_TOOL_OPTIONS) from env to java
|
||||
export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always
|
||||
SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
|
||||
SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG)
|
||||
SBT_NON_THIN = $(subst $(SBT_CLIENT_FLAG),,$(SBT))
|
||||
export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always -Dsbt.supershell=false -Dsbt.server.forcestart=true
|
||||
SBT ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
|
||||
|
||||
# (1) - classpath of the fat jar
|
||||
# (2) - main class
|
||||
# (3) - main class arguments
|
||||
define run_jar_scala_main
|
||||
cd $(base_dir) && java -cp $(1) $(2) $(3)
|
||||
endef
|
||||
|
||||
# (1) - sbt project
|
||||
# (2) - main class
|
||||
# (3) - main class arguments
|
||||
define run_scala_main
|
||||
cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
|
||||
endef
|
||||
|
||||
# (1) - sbt project to assemble
|
||||
# (2) - classpath file(s) to create
|
||||
define run_sbt_assembly
|
||||
cd $(base_dir) && $(SBT) ";project $(1); set assembly / assemblyOutputPath := file(\"$(2)\"); assembly"
|
||||
endef
|
||||
|
||||
FIRRTL_LOGLEVEL ?= error
|
||||
|
||||
#########################################################################################
|
||||
|
||||
@@ -171,4 +171,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
|
||||
#########################################################################################
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
|
||||
rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(CLASSPATH_CACHE) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
|
||||
|
||||
Reference in New Issue
Block a user