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Fixes for in-tree barstools

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This commit is contained in:
Jerry Zhao
2024-04-19 11:30:15 -07:00
parent d7060f4b5a
commit 9436aea1e8
26 changed files with 40 additions and 43 deletions
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2
.github/scripts/check-commit.sh vendored
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@@ -92,7 +92,7 @@ dir="software"
branches=("master" "dev")
search
submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
submodules=("DRAMSim2" "axe" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
dir="tools"
branches=("master" "dev" "main")
search

9
build.sbt
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@@ -158,7 +158,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
.settings(commonSettings)
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
@@ -256,13 +256,10 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell")
.settings(chiselSettings)
.settings(commonSettings)
lazy val tapeout = (project in file("./tools/barstools/"))
lazy val tapeout = (project in file("./tools/tapeout/"))
.settings(chiselSettings)
.settings(commonSettings)
.settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2"))
lazy val fixedpoint = (project in file("./tools/fixedpoint/"))
.settings(chiselSettings)

16
common.mk
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@@ -91,9 +91,9 @@ VLOG_EXT = sv v
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT))
CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT))
BARSTOOLS_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/barstools)
BARSTOOLS_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(SCALA_EXT))
BARSTOOLS_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(VLOG_EXT))
TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout)
TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT))
TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT))
# This assumes no SBT meta-build sources
SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools)
SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties
@@ -127,7 +127,7 @@ $(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEP
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
# order only dependency between sbt runs needed to avoid concurrent sbt runs
$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(BARSTOOLS_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
@@ -165,7 +165,7 @@ define sfc_extra_low_transforms_anno_contents
[
{
"class": "firrtl.stage.RunFirrtlTransformAnnotation",
"transform": "barstools.tapeout.transforms.ExtraLowTransforms"
"transform": "tapeout.transforms.ExtraLowTransforms"
}
]
endef
@@ -232,7 +232,7 @@ $(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL)
$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS)
rm -rf $(GEN_COLLATERAL_DIR)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.transforms.GenerateModelStageMain,\
--no-dedup \
--output-file $(SFC_FIRRTL_BASENAME) \
--output-annotation-file $(SFC_ANNO_FILE) \
@@ -297,12 +297,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
TOP_MACROCOMPILER_MODE ?= --mode synflops
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR)
MODEL_MACROCOMPILER_MODE = --mode synflops
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR)
########################################################################################

2
docs/Customization/Custom-Chisel.rst
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@@ -59,7 +59,7 @@ should look something like this:
.. code-block:: scala
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
sha3, dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
yourproject, // <- added to the middle of the list for simplicity

2
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleI
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import barstools.iocell.chisel._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))

2
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -7,7 +7,7 @@ import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import barstools.iocell.chisel._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector

2
generators/chipyard/src/main/scala/example/CustomChipTop.scala
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@@ -6,7 +6,7 @@ import chipyard.iobinders._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy.{InModuleBody}
import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
import barstools.iocell.chisel._
import chipyard.iocell._
import chipyard._
import chipyard.harness.{BuildTop}
import sifive.blocks.devices.uart._

2
generators/chipyard/src/main/scala/example/FlatChipTop.scala
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@@ -13,7 +13,7 @@ import chipyard.{BuildSystem, DigitalTop}
import chipyard.harness.{BuildTop}
import chipyard.clocking._
import chipyard.iobinders._
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.serdes.{SerialTLKey}
class WithFlatChipTop extends Config((site, here, up) => {

2
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.devices.debug.{SimJTAG}
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.dram.{SimDRAM}
import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
import testchipip.soc.{TestchipSimDTM}

2
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
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@@ -27,7 +27,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}

4
generators/chipyard/src/main/scala/iocell/Analog.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details
package barstools.iocell.chisel
package chipyard.iocell
import chisel3._
import chisel3.util.{HasBlackBoxResource}
@@ -10,7 +10,7 @@ class AnalogConst(value: Int, width: Int = 1)
extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width)))
with HasBlackBoxResource {
val io = IO(new Bundle { val io = Analog(width.W) })
addResource("/barstools/iocell/vsrc/Analog.v")
addResource("/vsrc/Analog.v")
}
object AnalogConst {

2
generators/chipyard/src/main/scala/iocell/IOCell.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details
package barstools.iocell.chisel
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}

2
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -26,7 +26,7 @@ import firesim.configs.MemModelKey
import tracegen.{TraceGenSystemModuleImp}
import cva6.CVA6Tile
import barstools.iocell.chisel._
import chipyard.iocell._
import chipyard.iobinders._
import chipyard._
import chipyard.harness._

2
scripts/tutorial-patches/build.sbt.patch
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@@ -5,7 +5,7 @@ index c3be6161..2a6d7160 100644
@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+ //sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,

2
tools/tapeout/src/main/scala/macros/CostMetric.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details.
package barstools.macros
package tapeout.macros
/** Trait which can calculate the cost of compiling a memory against a certain
* library memory macro using a cost function.

4
tools/tapeout/src/main/scala/macros/MacroCompiler.scala
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@@ -5,9 +5,9 @@
* lib - technology SRAM(s) to use to compile mem
*/
package barstools.macros
package tapeout.macros
import barstools.macros.Utils._
import tapeout.macros.Utils._
import firrtl.Utils.{one, zero, BoolType}
import firrtl.annotations._
import firrtl.ir._

4
tools/tapeout/src/main/scala/macros/SynFlopsPass.scala
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@@ -1,8 +1,8 @@
// See LICENSE for license details.
package barstools.macros
package tapeout.macros
import barstools.macros.Utils._
import tapeout.macros.Utils._
import firrtl.Utils.{one, zero}
import firrtl._
import firrtl.ir._

2
tools/tapeout/src/main/scala/macros/Utils.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details.
package barstools.macros
package tapeout.macros
import firrtl.Utils.BoolType
import firrtl.ir._

2
tools/tapeout/src/main/scala/transforms/ExtraTransforms.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details.
package barstools.tapeout.transforms
package tapeout.transforms
import firrtl.Mappers._
import firrtl._

4
tools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala
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@@ -1,6 +1,6 @@
package barstools.tapeout.transforms
package tapeout.transforms
import barstools.tapeout.transforms.stage._
import tapeout.transforms.stage._
import firrtl._
import firrtl.annotations._
import firrtl.ir._

2
tools/tapeout/src/main/scala/transforms/retime/Retime.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details.
package barstools.tapeout.transforms.retime
package tapeout.transforms.retime
import chisel3.experimental.RunFirrtlTransform
import firrtl.annotations._

4
tools/tapeout/src/main/scala/transforms/stage/TapeoutStage.scala
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@@ -1,8 +1,8 @@
// See LICENSE for license details.
package barstools.tapeout.transforms.stage
package tapeout.transforms.stage
import barstools.tapeout.transforms.GenerateModelStageMain
import tapeout.transforms.GenerateModelStageMain
import chisel3.stage.ChiselCli
import firrtl.stage.{RunFirrtlTransformAnnotation}
import firrtl.AnnotationSeq

2
tools/tapeout/src/main/scala/transforms/utils/FileUtils.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details.
package barstools.tapeout.transforms.utils
package tapeout.transforms.utils
import chisel3.experimental.{annotate, ChiselAnnotation}
import firrtl._

2
tools/tapeout/src/main/scala/transforms/utils/LowerAnnotations.scala
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@@ -1,4 +1,4 @@
package barstools.tapeout.transforms.utils
package tapeout.transforms.utils
object LowerName {
def apply(s: String): String = s.replace(".", "_").replace("[", "_").replace("]", "")

2
tools/tapeout/src/main/scala/transforms/utils/ProgrammaticBundle.scala
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@@ -1,4 +1,4 @@
package barstools.tapeout.transforms.utils
package tapeout.transforms.utils
import chisel3._

2
tools/tapeout/src/main/scala/transforms/utils/YamlHelpers.scala
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@@ -1,4 +1,4 @@
package barstools.tapeout.transforms.utils
package tapeout.transforms.utils
import firrtl.FileUtils
import net.jcazevedo.moultingyaml._