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Same as Makefile

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This commit is contained in:
Sagar Karandikar
2023-02-15 18:26:30 -08:00
committed by GitHub
parent 86abfd1e73
commit 97f576da2a
1 changed files with 1 additions and 1 deletions
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vlsi/sim.mk
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@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $(shell cat $(sim_common_files)); do \
for x in $$(cat $(sim_common_files)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@