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Update docs on bringup sims

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This commit is contained in:
Jerry Zhao
2023-09-20 11:44:43 -07:00
parent 57ee757016
commit 9ab5067e35
2 changed files with 13 additions and 19 deletions
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25
docs/Advanced-Concepts/Chip-Communication.rst
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@@ -183,28 +183,21 @@ This new setup (shown below) is a typical Chipyard test chip setup:
Simulation Setup of the Example Test Chip
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To test this type of configuration (TSI/memory transactions over the serial-link), most of the same TSI collateral
would be used.
The main difference is that the TileLink-to-AXI converters and simulated AXI memory resides on the other side of the
serial-link.
The standard test-chip bringup procedure tethers the chip to a FPGA config with serialized tilelink.
.. image:: ../_static/images/chip-bringup-simulation.png
.. note::
Here the simulated AXI memory and the converters can be in a different clock domain in the test harness
than the reference clock of the DUT.
For example, the DUT can be clocked at 3.2GHz while the simulated AXI memory can be clocked at 1GHz.
This functionality is done in the harness binder that instantiates the TSI collateral, TL-to-AXI converters,
and simulated AXI memory.
See :ref:`Advanced-Concepts/Harness-Clocks:Creating Clocks in the Test Harness` on how to generate a clock
in a harness binder.
The entire bringup procedure can be simulated using the Multi-ChipTop simulation feature, where
one ``ChipTop`` is the design-to-be-taped-out, while the other is the FPGA bringup design.
This type of simulation setup is done in the following multi-clock configuration:
This system can be generated and simulated with the following example configuration, which marries
a ``ChipLikeRocketConfig`` (the design to be taped-out) with the ``ChipBringupHostConfig`` (the FPGA
bringup design).
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/ChipConfigs.scala
:language: scala
:start-after: DOC include start: MulticlockAXIOverSerialConfig
:end-before: DOC include end: MulticlockAXIOverSerialConfig
:start-after: DOC include start: TetheredChipLikeRocketConfig
:end-before: DOC include end: TetheredChipLikeRocketConfig
Softcore-driven Bringup Setup of the Example Test Chip after Tapeout
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

7
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -89,12 +89,13 @@ class ChipBringupHostConfig extends Config(
// Base is the no-cores config
new chipyard.NoCoresConfig)
// DOC include start: TetheredChipLikeRocketConfig
class TetheredChipLikeRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute freqs for sims in the harness
new chipyard.harness.WithMultiChipSerialTL(0, 1) ++ // connect the serial-tl ports of the chips together
new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++ // ChipTop0 is the design-to-be-taped-out
new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig)) // ChipTop1 is the bringup design
// DOC include end: TetheredChipLikeRocketConfig
// Verilator does not initialize some of the async-reset reset-synchronizer
// flops properly, so this config disables them.