Inject MMCDevice into TLSPI Node
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@@ -6,7 +6,7 @@ import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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@@ -20,7 +20,6 @@ import sifive.fpgashells.shell.{DesignKey}
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import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD}
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import chipyard.{BuildTop}
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import chipyard.fpga.vcu118.bringup.{BringupGPIOs}
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import chipyard.harness._
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@@ -29,7 +28,12 @@ class WithBringupPeripherals extends Config((site, here, up) => {
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UARTParams(address = BigInt(0x64000000L)),
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UARTParams(address = BigInt(0x64003000L)))
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case PeripherySPIKey => List(
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SPIParams(rAddress = BigInt(0x64001000L)),
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SPIParams(rAddress = BigInt(0x64001000L),
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injectFunc = Some((spi: TLSPI) => {
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ResourceBinding {
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Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0))
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}
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})),
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SPIParams(rAddress = BigInt(0x64004000L)))
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case VCU118ShellPMOD => "SDIO"
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case PeripheryI2CKey => List(
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@@ -59,18 +59,6 @@ class WithSPIIOPassthrough extends OverrideIOBinder({
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}
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})
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//class WithMMCSPIDTS extends OverrideIOBinder({
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// (system: HasPeripherySPI) => {
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//
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// val mmcDev = new MMCDevice(system.tlspi.head.device, 1)
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// ResourceBinding {
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// Resource(mmcDev, "reg").bind(ResourceAddress(0))
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// }
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//
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// (Nil, Nil)
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// }
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//})
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class WithI2CIOPassthrough extends OverrideIOBinder({
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(system: HasPeripheryI2CModuleImp) => {
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val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") }
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Submodule generators/sifive-blocks updated: 413e0a88a4...ed9f63f9f5
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