add changes Alon requested

docs/Customization/Memory-Hierarchy.rst

@@ -58,7 +58,7 @@ and the number of banks must be powers of 2.
         new RocketConfig)
 
 The Broadcast Hub
-----------------
+-----------------
 
 If you do not want to use the L2 cache (say, for a resource-limited embedded
 design), you can create a configuration without it. Instead of using the L2
@@ -102,3 +102,11 @@ number of DRAM channels is restricted to powers of two.
     class DualChannelRocketConfig extends Config(
         new WithNMemoryChannels(2) ++
         new RocketConfig)
+
+In VCS and Verilator simulation, the DRAM is simulated using the
+``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each
+memory channel.
+
+If you want a more realistic memory simulation, you can use FireSim, which
+can simulate the timing of DDR3 controllers. More documentation on FireSim
+memory models is available in the `FireSim docs <https://docs.fires.im/en/latest/>`_.

docs/Generators/RocketChip.rst

@@ -1,8 +1,13 @@
 RocketChip
 ==========
 
-RocketChip is an SoC generator supported by SiFive. Chipyard uses RocketChip
-as the basis for producing a RISC-V SoC including Rocket, BOOM, and/or Hwacha.
+RocketChip is an SoC generator developed at Berkeley and now supported by
+SiFive. Chipyard uses RocketChip as the basis for producing a RISC-V SoC.
+
+RocketChip is distinct from Rocket, the in-order RISC-V CPU generator.
+RocketChip includes many parts of the SoC besides the CPU. Though RocketChip
+uses Rocket CPUs by default, it can also be configured to use the BOOM
+out-of-order core generator or some other custom CPU generator instead.
 
 A detailed diagram of a typical RocketChip system is shown below.
 
@@ -11,8 +16,9 @@ A detailed diagram of a typical RocketChip system is shown below.
 Tiles
 -----
 
-This is a dual-core ``Rocket`` system. Each ``Rocket`` core is grouped with a
-page-table walker, L1 instruction cache, and L1 data cache into a ``RocketTile``.
+The diagram shows a dual-core ``Rocket`` system. Each ``Rocket`` core is
+grouped with a page-table walker, L1 instruction cache, and L1 data cache into
+a ``RocketTile``.
 
 The ``Rocket`` core can also be swapped for a ``BOOM`` core. Each tile can
 also be configured with a RoCC accelerator that connects to the core as a

docs/TileLink-Diplomacy-Reference/index.rst

@@ -7,7 +7,8 @@ peripherals, and DMA devices communicate with each other.
 
 RocketChip's TileLink implementation is built on top of Diplomacy, a framework
 for exchanging configuration information among Chisel generators in a two-phase
-elaboration scheme.
+elaboration scheme. For a detailed explanation of Diplomacy, see `the paper
+by Cook, Terpstra, and Lee <https://carrv.github.io/2017/papers/cook-diplomacy-carrv2017.pdf>`_.
 
 A brief overview of how to connect simple TileLink widgets can be found
 in the :ref:`Adding-an-Accelerator` section. This section will provide a
@@ -15,7 +16,7 @@ detailed reference for the TileLink and Diplomacy functionality provided by
 RocketChip.
 
 A detailed specification of the TileLink 1.7 protocol can be found on the
-`SiFive website <https://sifive.cdn.prismic.io/sifive%2F57f93ecf-2c42-46f7-9818-bcdd7d39400a_tilelink-spec-1.7.1.pdf>`.
+`SiFive website <https://sifive.cdn.prismic.io/sifive%2F57f93ecf-2c42-46f7-9818-bcdd7d39400a_tilelink-spec-1.7.1.pdf>`_.
 
 
 .. toctree::