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[firechip] Update regfile optimization mixins

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This commit is contained in:
David Biancolin
2019-09-09 06:41:15 +00:00
parent d4be303df5
commit 9bf174afb3
2 changed files with 13 additions and 16 deletions
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13
generators/firechip/src/main/scala/TargetMixins.scala
View File

@@ -105,10 +105,10 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
}
trait CanHaveBoomMultiCycleRegfileImp {
val outer: boom.system.BoomRocketSubsystem
val cores = outer.boomTiles.map(tile => tile.module.core)
cores.foreach({ core =>
trait CanHaveMultiCycleRegfileImp {
val outer: utilities.HasBoomAndRocketTiles
val boomCores = outer.boomTiles.map(tile => tile.module.core)
boomCores.foreach({ core =>
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
@@ -118,11 +118,8 @@ trait CanHaveBoomMultiCycleRegfileImp {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
}
})
})
}
trait CanHaveRocketMultiCycleRegfileImp {
val outer: RocketSubsystem
outer.rocketTiles.foreach({ tile =>
annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))

16
generators/firechip/src/main/scala/Targets.scala
View File

@@ -31,7 +31,7 @@ import java.io.File
* determine which driver to build.
*******************************************************************************/
class FireSim(implicit p: Parameters) extends RocketSubsystem
class FireSim(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM
@@ -45,7 +45,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem
override lazy val module = new FireSimModuleImp(this)
}
class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
class FireSimModuleImp[+L <: FireSim](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
@@ -55,10 +55,10 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
with HasPeripheryIceNICModuleImpValidOnly
with HasPeripheryBlockDeviceModuleImp
with HasTraceIOImp
with CanHaveRocketMultiCycleRegfileImp
with CanHaveMultiCycleRegfileImp
class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
class FireSimNoNIC(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM
@@ -71,7 +71,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
override lazy val module = new FireSimNoNICModuleImp(this)
}
class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l)
class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
@@ -80,7 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
with HasPeripheryUARTModuleImp
with HasPeripheryBlockDeviceModuleImp
with HasTraceIOImp
with CanHaveRocketMultiCycleRegfileImp
with CanHaveMultiCycleRegfileImp
class FireBoom(implicit p: Parameters) extends Subsystem
@@ -108,7 +108,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
with HasPeripheryBlockDeviceModuleImp
with HasTraceIOImp
with ExcludeInvalidBoomAssertions
with CanHaveBoomMultiCycleRegfileImp
with CanHaveMultiCycleRegfileImp
class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
@@ -133,7 +133,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleI
with HasPeripheryBlockDeviceModuleImp
with HasTraceIOImp
with ExcludeInvalidBoomAssertions
with CanHaveBoomMultiCycleRegfileImp
with CanHaveMultiCycleRegfileImp
case object NumNodes extends Field[Int]