[temp] Following RC's way to build Chisel from source or Maven [ci skip]

This commit is contained in:
abejgonzalez
2020-11-16 22:24:18 -08:00
parent 70d43210d8
commit 9d9813fe0a
2 changed files with 21 additions and 6 deletions

View File

@@ -1,2 +1,2 @@
-Dsbt.sourcemode=true
-Dsbt.workspace=$PWD
-Dsbt.workspace=$PWD/tools

View File

@@ -78,7 +78,15 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
// Subproject definitions begin
lazy val chisel = (project in file("tools/chisel3"))
// This needs to stay in sync with the chisel3 and firrtl git submodules
val chiselVersion = "3.4.0"
lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel")
lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion
// While not built from source, *must* be in sync with the chisel3 git submodule
// Building from source requires extending sbt-sriracha or a similar plugin and
// keeping scalaVersion in sync with chisel3 to the minor version
lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full
lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter"))
.settings(commonSettings)
@@ -87,7 +95,9 @@ lazy val treadle = (project in file("tools/treadle"))
.settings(commonSettings)
lazy val chisel_testers = (project in file("tools/chisel-testers"))
.dependsOn(chisel, firrtl_interpreter, treadle)
.sourceDependency(chiselRef, chiselLib)
.dependsOn(firrtl_interpreter, treadle)
.settings(addCompilerPlugin(chiselPluginLib))
.settings(
commonSettings,
libraryDependencies ++= Seq(
@@ -113,15 +123,18 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu
.settings(commonSettings)
lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.sourceDependency(chiselRef, chiselLib)
.dependsOn(hardfloat, rocketMacros, rocketConfig)
.settings(addCompilerPlugin(chiselPluginLib))
.settings(commonSettings)
.dependsOn(chisel, hardfloat, rocketMacros, rocketConfig)
lazy val testchipip = (project in file("generators/testchipip"))
.dependsOn(rocketchip, sifive_blocks)
.settings(commonSettings)
lazy val iocell = (project in file("./tools/barstools/iocell/"))
.dependsOn(chisel)
.sourceDependency(chiselRef, chiselLib)
.settings(addCompilerPlugin(chiselPluginLib))
.settings(commonSettings)
lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
@@ -184,7 +197,9 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/"))
.settings(commonSettings)
lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
.dependsOn(chisel, chisel_testers)
.sourceDependency(chiselRef, chiselLib)
.dependsOn(chisel_testers)
.settings(addCompilerPlugin(chiselPluginLib))
.settings(
commonSettings,
libraryDependencies ++= Seq(