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Add more configs for coalescer perf testing

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Add run-coalperfs.sh in sims/vcs for ease of testing (please delete this file in the future)
This commit is contained in:
Vamber Yang
2023-05-20 08:49:39 -07:00
parent 439a72f21b
commit 9efd72ee2b
2 changed files with 192 additions and 44 deletions
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223
generators/chipyard/src/main/scala/config/GPUConfig.scala
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@@ -10,8 +10,8 @@ class MemtraceCoreConfig extends Config(
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
new freechips.rocketchip.subsystem.WithCoalescer() ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=4) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
@@ -22,49 +22,17 @@ class MemtraceCoreConfig extends Config(
)
class MemtraceCore128SbusConfig extends Config(
// Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
/////////////////////////////////////////////////
/// Various Configs for perf testing (feel free to delete them later)
/////////////////////////////////////////////////
class MemtraceCore256SbusConfig extends Config(
// Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(256) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
//8 src id section
class MemtraceCoreNV64B8IdConfig extends Config(
class MemtraceCorePoXarConfig extends Config(
// Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithPriorityCoalXbar++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
@@ -72,4 +40,171 @@ class MemtraceCorePoXarConfig extends Config(
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
)
class MemtraceCoreNV128B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV256B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(256) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV512B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(512) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
//16 src id section
class MemtraceCoreNV64B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(64) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV128B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV256B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(256) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV512B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(512) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
// 32 ids sections
class MemtraceCoreNV64B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(64) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV128B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV256B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(256) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV512B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(512) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)

13
sims/vcs/run-coalperfs.sh Normal file
View File

@@ -0,0 +1,13 @@
#!/bin/bash
configurations=("MemtraceCoreNV64B8IdConfig" "MemtraceCoreNV128B8IdConfig" "MemtraceCoreNV256B8IdConfig" "MemtraceCoreNV512B8IdConfig" "MemtraceCoreNV64B16IdConfig" "MemtraceCoreNV128B16IdConfig" "MemtraceCoreNV256B16IdConfig" "MemtraceCoreNV512B16IdConfig" "MemtraceCoreNV64B32IdConfig" "MemtraceCoreNV128B32IdConfig" "MemtraceCoreNV256B32IdConfig" "MemtraceCoreNV512B32IdConfig")
rm -f coal_perf.txt
make clean
for config in "${configurations[@]}"; do
time=$(make CONFIG="$config" run-binary-debug BINARY=none | grep "simulation time" | awk '{print $NF}')
echo "($config, $time)" >> coal_perf.txt
done
cat coal_perf.txt