Bump rocket-chip + Added GPU mem tracer configs
This commit is contained in:
Vamber Yang
2
.github/actions/cleanup-conda/action.yml
vendored
2
.github/actions/cleanup-conda/action.yml
vendored
@@ -15,7 +15,7 @@ runs:
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conda env remove -n $env
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done
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fi
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IS_NUMBER_REGEX='[0-9]+$'
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IS_NUMBER_REGEX='^[0-9]+$'
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conda env list | awk '{print $1}' | tail -n +4 | while read envname; do
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ENV_DATE=$(echo $envname | sed "s/cy-[[:digit:]]\+-\(.*\)-\(riscv\|esp\)-tools/\1/")
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if ! [[ $ENV_DATE =~ $IS_NUMBER_REGEX ]]; then
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|
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2
.github/scripts/check-commit.sh
vendored
2
.github/scripts/check-commit.sh
vendored
@@ -12,9 +12,7 @@ source $SCRIPT_DIR/defaults.sh
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cd $LOCAL_CHIPYARD_DIR
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|
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# ignore the private vlsi submodules
|
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git config submodule.vlsi/hammer-cadence-plugins.update none
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git config submodule.vlsi/hammer-mentor-plugins.update none
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git config submodule.vlsi/hammer-synopsys-plugins.update none
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# initialize submodules and get the hashes
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git submodule update --init
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54
.github/workflows/chipyard-full-flow.yml
vendored
54
.github/workflows/chipyard-full-flow.yml
vendored
@@ -107,6 +107,60 @@ jobs:
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source env.sh
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cd sims/verilator
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make verilog
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- name: VLSI test
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run: |
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cd ${{ env.REMOTE_WORK_DIR }}
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eval "$(conda shell.bash hook)"
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source env.sh
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cd vlsi
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# NOTE: most conda installs are in separate conda envs because they mess up
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# each other's versions (for no apparent reason) and we need the latest versions
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conda config --add channels defaults
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conda config --add channels litex-hub
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# installs for example-sky130.yml
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conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
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git clone https://github.com/rahulk29/sram22_sky130_macros.git
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# installs for example-openroad.yml
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conda create -y --prefix ./.conda-yosys yosys=0.27_4_gb58664d44
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conda create -y --prefix ./.conda-openroad openroad=2.0_7070_g0264023b6
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conda create -y --prefix ./.conda-klayout klayout=0.28.5_98_g87e2def28
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conda create -y --prefix ./.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
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echo "# Tutorial configs" > tutorial.yml
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echo "# pdk" > tutorial.yml
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echo "technology.sky130.sky130A: $PWD/.conda-sky130/share/pdk/sky130A" >> tutorial.yml
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echo "technology.sky130.sram22_sky130_macros: $PWD/sram22_sky130_macros" >> tutorial.yml
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echo "" >> tutorial.yml
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echo "# tools" >> tutorial.yml
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echo "synthesis.yosys.yosys_bin: $PWD/.conda-yosys/bin/yosys" >> tutorial.yml
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echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> tutorial.yml
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echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml
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echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
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echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
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echo "" >> tutorial.yml
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echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
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echo "par.openroad.timing_driven: false" >> tutorial.yml
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echo "par.openroad.write_reports: false" >> tutorial.yml
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conda config --remove channels litex-hub
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conda config --remove channels defaults
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export tutorial=sky130-openroad
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export EXTRA_CONFS=tutorial.yml
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export VLSI_TOP=RocketTile
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make buildfile
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make syn
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# openroad freezes during some write commands after detailed route
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# so need to stop the flow & run last step separately
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make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
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make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
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make drc
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make lvs
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cleanup:
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name: cleanup
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29
.github/workflows/chipyard-run-tests.yml
vendored
29
.github/workflows/chipyard-run-tests.yml
vendored
@@ -390,6 +390,35 @@ jobs:
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||||
|
||||
##########################################################################
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chipyard-spike-gemmini-run-tests:
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name: chipyard-spike-gemmini-run-tests
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needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini
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runs-on: ferry
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steps:
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- name: Delete old checkout
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run: |
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ls -alh .
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rm -rf ${{ github.workspace }}/* || true
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rm -rf ${{ github.workspace }}/.* || true
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ls -alh .
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- name: Checkout
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uses: actions/checkout@v3
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- name: Git workaround
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uses: ./.github/actions/git-workaround
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- name: Create conda env
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uses: ./.github/actions/create-conda-env
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- name: Build Gemmini FireMarshal
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run: |
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conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
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cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force
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cd ${{ github.workspace }} && source ./scripts/fix-open-files.sh
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git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh
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cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json
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- name: Running Gemmini FireMarshal smoke test
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run: |
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conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
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cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json
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|
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chipyard-rocket-run-tests:
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name: chipyard-rocket-run-tests
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needs: prepare-chipyard-cores
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6
.gitmodules
vendored
6
.gitmodules
vendored
@@ -34,12 +34,6 @@
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[submodule "generators/sha3"]
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path = generators/sha3
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url = https://github.com/ucb-bar/sha3.git
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[submodule "vlsi/hammer-cadence-plugins"]
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path = vlsi/hammer-cadence-plugins
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url = https://github.com/ucb-bar/hammer-cadence-plugins.git
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[submodule "vlsi/hammer-synopsys-plugins"]
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path = vlsi/hammer-synopsys-plugins
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url = https://github.com/ucb-bar/hammer-synopsys-plugins.git
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[submodule "vlsi/hammer-mentor-plugins"]
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path = vlsi/hammer-mentor-plugins
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url = https://github.com/ucb-bar/hammer-mentor-plugins.git
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@@ -5,8 +5,6 @@ build:
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tools:
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python: "mambaforge-4.10"
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formats: all
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sphinx:
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configuration: docs/conf.py
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81
CHANGELOG.md
81
CHANGELOG.md
@@ -2,6 +2,87 @@
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||||
|
||||
This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
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||||
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## [1.9.0] - 2023-03-23
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||||
Faster FIRRTL build support work CIRCT. New software support for RISC-V GCC12 and Linux 6.2. Various bumps and fixes of all submodules.
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||||
### Added
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||||
* Add example ring-only NoC Config by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1325
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* Bump Gemmini by @hngenc, @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1276 https://github.com/ucb-bar/chipyard/pull/1326
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* Bump FireMarshal, Bump to newer RV toolchain (deprecate use of esp-tools for Gemmini) by @abejgonzalez, @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1284 https://github.com/ucb-bar/chipyard/pull/1304 https://github.com/ucb-bar/chipyard/pull/1306 https://github.com/ucb-bar/chipyard/pull/1327 https://github.com/ucb-bar/chipyard/pull/1334 https://github.com/ucb-bar/chipyard/pull/1335 https://github.com/ucb-bar/chipyard/pull/1344 https://github.com/ucb-bar/chipyard/pull/1394 https://github.com/ucb-bar/chipyard/pull/1403 https://github.com/ucb-bar/chipyard/pull/1415
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||||
* Add support for VC707 FPGA board by @Lorilandly in https://github.com/ucb-bar/chipyard/pull/1278
|
||||
* Fail simulations on TSI errors by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1288
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||||
* Add pre-commit support by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1294 https://github.com/ucb-bar/chipyard/pull/1310
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* Bump mempress by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1305
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* CIRCT Integration by @abejgonzalez, @joey0320 in https://github.com/ucb-bar/chipyard/pull/1239 https://github.com/ucb-bar/chipyard/pull/1312 https://github.com/ucb-bar/chipyard/pull/1372 https://github.com/ucb-bar/chipyard/pull/1396
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* Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1303
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||||
* Spike-as-a-Tile and use for co-simulation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1307 https://github.com/ucb-bar/chipyard/pull/1323 https://github.com/ucb-bar/chipyard/pull/1360
|
||||
* Add clone-tile configs by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1322
|
||||
* New Hammer by @harrisonliew in https://github.com/ucb-bar/chipyard/pull/1324 https://github.com/ucb-bar/chipyard/pull/1368 https://github.com/ucb-bar/chipyard/pull/1374 https://github.com/ucb-bar/chipyard/pull/1369 https://github.com/ucb-bar/chipyard/pull/1410
|
||||
* Config finder `make` target by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1328 https://github.com/ucb-bar/chipyard/pull/1381
|
||||
* Arty100T board + TSI-over-UART by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1345
|
||||
* Add graphml visualization section to docs by @schwarz-em in https://github.com/ucb-bar/chipyard/pull/1387
|
||||
* Add a frag./config for MMIO only FireSim bridges by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1393
|
||||
* Add log of chisel elaboration to generated src by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1400
|
||||
* Xcelium support by @sagark in https://github.com/ucb-bar/chipyard/pull/1386
|
||||
* Bump Sodor @a0u in https://github.com/ucb-bar/chipyard/pull/1338
|
||||
* Bump Constellation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1339
|
||||
|
||||
### Changed
|
||||
* remove RocketTilesKey by @SingularityKChen in https://github.com/ucb-bar/chipyard/pull/1264
|
||||
* Move setup script to scripts/, use a symlink at top-level by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1271
|
||||
* Decoupled sbus width from boom|hwacha|gemmini memory interface widths by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1273
|
||||
* Remove conda from build-toolchains-extra.sh by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1266
|
||||
* Rework build-setup | Add single-node CI by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1282
|
||||
* Switch simulators to C++17. by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1285
|
||||
* Init FPGA submodules in build-setup.sh by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1292
|
||||
* Stripped down rocket configs for FireSim testing by @t14916 in https://github.com/ucb-bar/chipyard/pull/1302
|
||||
* Add more minimal firesim configs for testing by @t14916 in https://github.com/ucb-bar/chipyard/pull/1313
|
||||
* Add workshop info to README.md by @sagark in https://github.com/ucb-bar/chipyard/pull/1314
|
||||
* Removed FireSim tests and harnesses by @nandor in https://github.com/ucb-bar/chipyard/pull/1317
|
||||
* Move boom's tracegen interface to boom submodule by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1331
|
||||
* Split up RocketConfigs.scala by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1340
|
||||
* Sky130/Openroad Tutorial Fixes by @nayiri-k in https://github.com/ucb-bar/chipyard/pull/1392
|
||||
* Testing VLSI commands for chipyard tutorial by @nayiri-k in https://github.com/ucb-bar/chipyard/pull/1395
|
||||
* Reduce test cases for noc-config in CI by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1359
|
||||
* Remove TLHelper, directly use tilelink node constructors by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1358
|
||||
* Remove chisel-testers submodule by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1378
|
||||
* Cache `.ivy2` and `.sbt` within Chipyard root directory by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1362
|
||||
|
||||
### Fixed
|
||||
* Remove extra parenthesis by @odxa20 in https://github.com/ucb-bar/chipyard/pull/1261
|
||||
* Fixed typo in Initial-Repo-Setup.rst by @PisonJay in https://github.com/ucb-bar/chipyard/pull/1269
|
||||
* fix: S-interpolator for assert, assume and printf by @SingularityKChen in https://github.com/ucb-bar/chipyard/pull/1242
|
||||
* Revert "fix: S-interpolator for assert, assume and printf" by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1272
|
||||
* changelog: fixed TinyRocketArtyConfig FPGA reset signal polarity (Please Backport) by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1257
|
||||
* Fix CY logo in README by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1295
|
||||
* More files to gitignore by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1297
|
||||
* Bump rocket-dsp-utils for ShiftRegisterMem fix. by @milovanovic in https://github.com/ucb-bar/chipyard/pull/1298
|
||||
* Set VLOGMODEL=MODEL by default in variables.mk by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1337
|
||||
* Fix compile breaking due to merge conflict by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1321
|
||||
* Makefile bug fixes by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1336
|
||||
* Fix Verilog Prerequisites + Ignore `mv` stdout by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1406
|
||||
* Fix Chisel hierarchy API - Fixes #1356 by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1361
|
||||
* Remove gen-collateral when rebuilding by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1342
|
||||
* Fix VLSI input files list emission to avoid bash "too many arguments" error by @sagark in https://github.com/ucb-bar/chipyard/pull/1348
|
||||
* Small build system improvements by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1349
|
||||
* Fix socket name length issues on CI by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1353
|
||||
* Fix TestDriver.v missing from gen-collateral after recompiling by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1354
|
||||
* Consolidate CI testing configs to improve CI runtime by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1352
|
||||
* Remove Duplicate Compiler Flags by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1351
|
||||
* fpga makefile clean fix by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1357
|
||||
* Fix newline in message in build-setup.sh by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1365
|
||||
* Update assert message if configs can't be split by `:` by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1373
|
||||
* Remove Duplicate Compiler Flags by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1367
|
||||
* Move more tmp/ folders to a unique location by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1382
|
||||
* Remove stale conda env's after 2 days by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1389
|
||||
* Match CY/FireSim deps | Unpin deps | Update lockfiles by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1391
|
||||
* Only support HTML docs by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1401
|
||||
* Only HTML docs v2 by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1402
|
||||
* Fix ANSI color output by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1407
|
||||
* Fix chisel elab errors not causing flow to stop by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1409
|
||||
* lean gemmini tutorial by @sagark in https://github.com/ucb-bar/chipyard/pull/1413
|
||||
|
||||
## [1.8.1] - 2022-10-18
|
||||
|
||||
Various fixes and improvements, bump FireSim to 1.15.1.
|
||||
|
||||
@@ -84,6 +84,7 @@ These additional publications cover many of the internal components used in Chip
|
||||
* **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192).
|
||||
* **VLSI**
|
||||
* **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html).
|
||||
* **Hammer**: H. Liew, et al., *DAC'22*. [PDF](https://dl.acm.org/doi/abs/10.1145/3489517.3530672).
|
||||
|
||||
## Acknowledgements
|
||||
|
||||
|
||||
17
common.mk
17
common.mk
@@ -18,7 +18,7 @@ HELP_COMPILATION_VARIABLES += \
|
||||
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
|
||||
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
|
||||
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
|
||||
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \
|
||||
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
|
||||
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
|
||||
" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler"
|
||||
|
||||
@@ -57,6 +57,7 @@ HELP_COMMANDS += \
|
||||
# see HELP_COMPILATION_VARIABLES
|
||||
#########################################################################################
|
||||
include $(base_dir)/generators/cva6/cva6.mk
|
||||
include $(base_dir)/generators/ibex/ibex.mk
|
||||
include $(base_dir)/generators/tracegen/tracegen.mk
|
||||
include $(base_dir)/generators/nvdla/nvdla.mk
|
||||
include $(base_dir)/tools/dromajo/dromajo.mk
|
||||
@@ -104,14 +105,14 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
|
||||
# create firrtl file rule and variables
|
||||
#########################################################################################
|
||||
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
|
||||
$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
|
||||
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
|
||||
mkdir -p $(build_dir)
|
||||
$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
|
||||
(set -o pipefail && $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
|
||||
--target-dir $(build_dir) \
|
||||
--name $(long_name) \
|
||||
--top-module $(MODEL_PACKAGE).$(MODEL) \
|
||||
--legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \
|
||||
$(EXTRA_CHISEL_OPTIONS))
|
||||
$(EXTRA_CHISEL_OPTIONS)) | tee $(CHISEL_LOG_FILE))
|
||||
|
||||
define mfc_extra_anno_contents
|
||||
[
|
||||
@@ -174,7 +175,7 @@ MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVar
|
||||
# hack: lower to low firrtl if Fixed types are found
|
||||
# hack: when using dontTouch, io.cpu annotations are not removed by SFC,
|
||||
# hence we remove them manually by using jq before passing them to firtool
|
||||
$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
|
||||
$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(VLOG_SOURCES)
|
||||
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
|
||||
$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
|
||||
$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
|
||||
@@ -191,7 +192,7 @@ endif
|
||||
if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
|
||||
|
||||
$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
|
||||
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
|
||||
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
|
||||
rm -rf $(GEN_COLLATERAL_DIR)
|
||||
$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
|
||||
--no-dedup \
|
||||
@@ -204,7 +205,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE
|
||||
--allow-unrecognized-annotations \
|
||||
-X $(SFC_LEVEL) \
|
||||
$(EXTRA_FIRRTL_OPTIONS))
|
||||
-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
|
||||
-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL
|
||||
@if [ $(SFC_LEVEL) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json; fi
|
||||
@if [ $(SFC_LEVEL) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
|
||||
@if [ $(SFC_LEVEL) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
|
||||
@@ -226,7 +227,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE
|
||||
--split-verilog \
|
||||
-o $(GEN_COLLATERAL_DIR) \
|
||||
$(SFC_FIRRTL_FILE)
|
||||
-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF)
|
||||
-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null
|
||||
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
|
||||
# DOC include end: FirrtlCompiler
|
||||
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
channels:
|
||||
- ucb-bar
|
||||
- conda-forge
|
||||
- litex-hub
|
||||
- nodefaults
|
||||
|
||||
platforms:
|
||||
@@ -46,7 +47,6 @@ dependencies:
|
||||
- doit>=0.34.0
|
||||
- gitpython
|
||||
- humanfriendly
|
||||
- e2fsprogs
|
||||
- ctags
|
||||
- bison
|
||||
- flex
|
||||
@@ -101,8 +101,9 @@ dependencies:
|
||||
|
||||
# hammer packages
|
||||
- sty
|
||||
- open_pdks.sky130a
|
||||
- pip:
|
||||
- hammer-vlsi[asap7]==1.0.1
|
||||
- hammer-vlsi[asap7]==1.1.0
|
||||
|
||||
# doc requirements
|
||||
- sphinx
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,7 @@
|
||||
channels:
|
||||
- ucb-bar
|
||||
- conda-forge
|
||||
- litex-hub
|
||||
- nodefaults
|
||||
|
||||
platforms:
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
channels:
|
||||
- ucb-bar
|
||||
- conda-forge
|
||||
- litex-hub
|
||||
- nodefaults
|
||||
|
||||
platforms:
|
||||
@@ -14,4 +15,4 @@ dependencies:
|
||||
# https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
|
||||
# documentation on package_spec syntax for constraining versions
|
||||
|
||||
- riscv-tools=1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
|
||||
- riscv-tools=1.0.3 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
|
||||
|
||||
@@ -18,6 +18,13 @@ The ``IOBinders`` are responsible for instantiating the IO cells for ``ChipTop``
|
||||
The ``HarnessBinders`` are responsible for instantiating test harness collateral that connects to the ``ChipTop`` ports.
|
||||
Most types of devices and testing collateral can be instantiated using custom ``IOBinders`` and ``HarnessBinders``.
|
||||
|
||||
Custom ChipTops
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The default standard ``ChipTop`` provides a mimimal, barebones template for ``IOBinders`` to generate IOCells around ``DigitalTop`` traits.
|
||||
For tapeouts, integrating Analog IP, or other non-standard use cases, Chipyard supports specifying a custom ``ChipTop`` using the ``BuildTop`` key.
|
||||
An example of a custom ChipTop which uses non-standard IOCells is provided in `generators/chipyard/src/main/scala/example/CustomChipTop.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/example/CustomChipTop.scala>`__
|
||||
|
||||
|
||||
System/DigitalTop
|
||||
-------------------------
|
||||
|
||||
@@ -10,15 +10,18 @@ Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chi
|
||||
|
||||
The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler
|
||||
------------------------------------------------------
|
||||
In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler(SFC) and the MLIR FIRRTL compiler(MFC).
|
||||
They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster. In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
|
||||
compile CHIRRTL into Verilog(as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
|
||||
In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC).
|
||||
They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
|
||||
compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
|
||||
we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
|
||||
|
||||
For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/.
|
||||
|
||||
Where to add transforms
|
||||
-----------------------
|
||||
|
||||
In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Harness" file containing the test harness, which instantiates the DUT.
|
||||
The "Harness" file does not contain the DUT's module definition or any of its submodules.
|
||||
In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Model" file containing the test harness, which instantiates the DUT.
|
||||
The "Model" file does not contain the DUT's module definition or any of its submodules.
|
||||
This is done by the ``tapeout`` SBT project (located in ``tools/barstools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms).
|
||||
|
||||
.. literalinclude:: ../../common.mk
|
||||
|
||||
@@ -32,4 +32,21 @@ In this configuration, Spike is cache-coherent, and communicates with the uncore
|
||||
|
||||
make CONFIG=SpikeConfig run-binary BINARY=hello.riscv
|
||||
|
||||
Spike-as-a-Tile also supports Tightly-Coupled-Memory (TCM) for the SpikeTile, in which the main system memory is entirely modeled
|
||||
within the Spike tile, allowing for very fast simulatoin performance.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv
|
||||
|
||||
Spike-as-a-Tile can be configured with custom IPC, commit logging, and other behaviors. Spike-specific flags can be added as plusargs to ``EXTRA_SIM_FLAGS``
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=SpikeUltraFastConfig run-binary-hex BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug"
|
||||
|
||||
|
||||
* ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation.
|
||||
* ``+spike-fast-clint``: Enables fast-forwarding through WFI stalls by generating fake timer interrupts
|
||||
* ``+spike-debug``: Enables debug Spike logging
|
||||
* ``+spike-verbose``: Enables Spike commit-log generation
|
||||
|
||||
@@ -3,8 +3,10 @@ FIRRTL
|
||||
|
||||
`FIRRTL <https://github.com/freechipsproject/firrtl>`__ is an intermediate representation of your circuit.
|
||||
It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog.
|
||||
Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations.
|
||||
Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which passes the circuit through a series of circuit-level transformations.
|
||||
An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
|
||||
Once the transformations are done, a Verilog file is emitted and the build process is done.
|
||||
|
||||
For more information on please visit their `website <https://chisel-lang.org/firrtl/>`__.
|
||||
To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section.
|
||||
|
||||
For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
|
||||
ASAP7 Tutorial
|
||||
==============
|
||||
The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
|
||||
The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Mentor tool plugin submodule, which is needed for DRC & LVS.
|
||||
|
||||
Project Structure
|
||||
-----------------
|
||||
@@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre:
|
||||
.. code-block:: shell
|
||||
|
||||
make drc CONFIG=TinyRocketConfig
|
||||
./build/drc-rundir/generated-scripts/view-drc
|
||||
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc
|
||||
make lvs CONFIG=TinyRocketConfig
|
||||
./build/lvs-rundir/generated-scripts/view-lvs
|
||||
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs
|
||||
|
||||
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__.
|
||||
Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors.
|
||||
|
||||
@@ -162,7 +162,7 @@ Simulation-exacted power estimation often requires a dedicated testharness for t
|
||||
The simulation-extracted power estimation flow implicitly uses Hammer's gate-level simulation flow (in order to generate the ``saif`` activity data file). This gate-level simulation flow can also be run independantly from the power estimation flow using the ``make sim-par`` command.
|
||||
|
||||
|
||||
.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Incisive is work-in-progress)
|
||||
.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Xcelium is work-in-progress)
|
||||
|
||||
|
||||
Signoff
|
||||
|
||||
@@ -46,7 +46,7 @@ The current set of all available Hammer APIs is codified `here <https://github.c
|
||||
Tool Plugins
|
||||
============
|
||||
|
||||
Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor plugins repositories with permission from the respective CAD tool vendor.
|
||||
Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Mentor plugins submodule with permission from the respective CAD tool vendor.
|
||||
The types of tools (by Hammer names) supported currently include:
|
||||
|
||||
* synthesis
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
.. _sky130-commercial-tutorial:
|
||||
|
||||
Sky130 Tutorial
|
||||
===============
|
||||
The ``vlsi`` folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
|
||||
Sky130 Commercial Tutorial
|
||||
==========================
|
||||
The ``vlsi`` folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Mentor tool plugin submodule, which is needed for DRC & LVS.
|
||||
|
||||
Project Structure
|
||||
-----------------
|
||||
@@ -47,7 +47,23 @@ Prerequisites
|
||||
|
||||
* Python 3.9+
|
||||
* Genus, Innovus, Voltus, VCS, and Calibre licenses
|
||||
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
|
||||
* Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
|
||||
* `Sram22 Sky130 SRAM macros <https://github.com/rahulk29/sram22_sky130_macros>`__
|
||||
|
||||
* These SRAM macros were generated using the `Sram22 SRAM generator <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
|
||||
|
||||
Quick Prerequisite Setup
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
As of recently, the Sky130A PDK may be installed via conda.
|
||||
The prerequisite setup for this tutorial may eventually be scripted, but for now the directions to set them up are below.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
# download all files for Sky130A PDK
|
||||
conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
|
||||
# clone the SRAM22 Sky130 SRAM macros
|
||||
git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
|
||||
|
||||
|
||||
Initial Setup
|
||||
-------------
|
||||
@@ -59,6 +75,38 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
|
||||
|
||||
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
|
||||
|
||||
Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
|
||||
We will summarize a few files in this directory that will be important for the rest of the tutorial.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
cd ~chipyard/vlsi
|
||||
|
||||
example-vlsi-sky130
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
|
||||
|
||||
|
||||
example-sky130.yml
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
|
||||
|
||||
Add the following YAML keys to the top of this file to specify the location of the Sky130A PDK and SRAM macros.
|
||||
|
||||
.. code-block:: yaml
|
||||
|
||||
# all ~ should be replaced with absolute paths to these directories
|
||||
# technology paths
|
||||
technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A
|
||||
technology.sky130.sram22_sky130_macros: ~/sram22_sky130_macros
|
||||
|
||||
|
||||
example-tools.yml
|
||||
^^^^^^^^^^^^^^^^^
|
||||
This contains the Hammer configuration for a commercial tool flow.
|
||||
It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre).
|
||||
|
||||
|
||||
Building the Design
|
||||
--------------------
|
||||
To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
|
||||
@@ -71,12 +119,21 @@ The command ``make buildfile`` generates a set of Make targets in ``build/hammer
|
||||
It needs to be re-run if environment variables are changed.
|
||||
It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
|
||||
|
||||
The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources
|
||||
and (2) the mapping of memory instances in the design to SRAM macros;
|
||||
all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory.
|
||||
Note that the files in ``generated-src`` vary for each tool/technology flow.
|
||||
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
|
||||
(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
|
||||
chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
|
||||
|
||||
|
||||
For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-commercial``,
|
||||
which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
|
||||
|
||||
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
|
||||
* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
|
||||
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described below
|
||||
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described above
|
||||
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
|
||||
* ``VLSI_OBJ_DIR=build-sky130-commercial`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
|
||||
* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
|
||||
@@ -84,24 +141,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
|
||||
Running the VLSI Flow
|
||||
---------------------
|
||||
|
||||
example-vlsi-sky130
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
|
||||
|
||||
|
||||
example-sky130.yml
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
|
||||
|
||||
First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
|
||||
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
|
||||
for details about the PDK setup.
|
||||
|
||||
example-tools.yml
|
||||
^^^^^^^^^^^^^^^^^
|
||||
This contains the Hammer configuration for a commercial tool flow.
|
||||
It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre).
|
||||
|
||||
Synthesis
|
||||
^^^^^^^^^
|
||||
.. code-block:: shell
|
||||
@@ -160,3 +199,20 @@ Post-P&R power and rail (IR drop) analysis is supported with Voltus:
|
||||
If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim-<syn/par>-debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform.
|
||||
|
||||
To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported.
|
||||
|
||||
|
||||
VLSI Flow Control
|
||||
^^^^^^^^^^^^^^^^^
|
||||
Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
# the following two statements are equivalent because the
|
||||
# extraction step immediately precedes the write_design step
|
||||
make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
|
||||
make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"
|
||||
|
||||
# example of re-running only floorplanning to test out a new floorplan configuration
|
||||
# the "-p file.yml" causes file.yml to override any previous yaml/json configurations
|
||||
make redo-par \
|
||||
HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-designs/sky130-openroad.yml"
|
||||
|
||||
@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
|
||||
|
||||
* ``env.yml``
|
||||
|
||||
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
|
||||
* This file is not used in this tutorial, but is required for the commercial tool flow. A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
|
||||
|
||||
* ``example-vlsi-sky130``
|
||||
|
||||
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
|
||||
|
||||
* ``example-sky130.yml``, ``example-openroad.yml``, ``example-designs/sky130-openroad.yml``
|
||||
|
||||
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
|
||||
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example Sky130 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
|
||||
|
||||
* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
|
||||
|
||||
@@ -48,12 +48,35 @@ Prerequisites
|
||||
* Python 3.9+
|
||||
* OpenROAD flow tools:
|
||||
|
||||
* Yosys (synthesis), install `from source <https://yosyshq.net/yosys/download.html>`__ or `using conda <https://anaconda.org/TimVideos/yosys>`__
|
||||
* OpenROAD (place-and-route), install `from source <https://openroad.readthedocs.io/en/latest/main/README.html#install-dependencies>`__
|
||||
* Magic (DRC), install `from source <http://www.opencircuitdesign.com/magic/install.html>`__
|
||||
* NetGen (LVS), install `from source <http://www.opencircuitdesign.com/netgen/install.html>`__ or `using conda <https://anaconda.org/conda-forge/netgen>`__
|
||||
* Yosys (synthesis), install `using conda <https://anaconda.org/litex-hub/yosys>`__ or `from source <https://yosyshq.net/yosys/download.html>`__
|
||||
* OpenROAD (place-and-route), install `using conda <https://anaconda.org/litex-hub/openroad>`__ (note that GUI is disabled in conda package) or `from source <https://openroad.readthedocs.io/en/latest/main/README.html#install-dependencies>`__
|
||||
* KLayout (DEF to GDSII conversion), install `using conda <https://anaconda.org/litex-hub/klayout>`__ or `from source <https://www.klayout.de/build.html>`__
|
||||
* Magic (DRC), , install `using conda <https://anaconda.org/litex-hub/magic>`__ or `from source <http://www.opencircuitdesign.com/magic/install.html>`__
|
||||
* NetGen (LVS), , install `using conda <https://anaconda.org/litex-hub/netgen>`__ or `from source <http://www.opencircuitdesign.com/netgen/install.html>`__
|
||||
|
||||
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
|
||||
* Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
|
||||
* `Sram22 Sky130 SRAM macros <https://github.com/rahulk29/sram22_sky130_macros>`__
|
||||
|
||||
* These SRAM macros were generated using the `Sram22 SRAM generator <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
|
||||
|
||||
Quick Prerequisite Setup
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
As of recently, most of the prerequisites of this tutorial may now be installed as conda packages.
|
||||
The prerequisite setup for this tutorial may eventually be scripted, but for now the directions to set them up are below.
|
||||
Note that we create a new conda environment for each tool because some of them have conflicting dependencies.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
# download all files for Sky130A PDK
|
||||
conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
|
||||
# clone the SRAM22 Sky130 SRAM macros
|
||||
git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
|
||||
|
||||
# install all VLSI tools
|
||||
conda create -c litex-hub --prefix ~/.conda-yosys yosys=0.27_4_gb58664d44
|
||||
conda create -c litex-hub --prefix ~/.conda-openroad openroad=2.0_7070_g0264023b6
|
||||
conda create -c litex-hub --prefix ~/.conda-klayout klayout=0.28.5_98_g87e2def28
|
||||
conda create -c litex-hub --prefix ~/.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
|
||||
|
||||
Initial Setup
|
||||
-------------
|
||||
@@ -66,31 +89,13 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
|
||||
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder,
|
||||
and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
|
||||
|
||||
Building the Design
|
||||
--------------------
|
||||
To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
|
||||
Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
|
||||
We will summarize a few files in this directory that will be important for the rest of the tutorial.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make buildfile tutorial=sky130-openroad
|
||||
cd ~chipyard/vlsi
|
||||
|
||||
The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
|
||||
It needs to be re-run if environment variables are changed.
|
||||
It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
|
||||
|
||||
For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``,
|
||||
which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
|
||||
|
||||
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
|
||||
* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
|
||||
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below
|
||||
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
|
||||
* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
|
||||
* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
|
||||
* ``ENABLE_CUSTOM_FIRRTL_PASS = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
|
||||
|
||||
Running the VLSI Flow
|
||||
---------------------
|
||||
|
||||
example-vlsi-sky130
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
@@ -101,16 +106,70 @@ example-sky130.yml
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
|
||||
|
||||
First, set ``technology.sky130.<sky130A, openram_lib>`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
|
||||
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
|
||||
for details about the PDK setup.
|
||||
Add the following YAML keys to the top of this file to specify the location of the Sky130A PDK and SRAM macros.
|
||||
|
||||
.. code-block:: yaml
|
||||
|
||||
# all ~ should be replaced with absolute paths to these directories
|
||||
# technology paths
|
||||
technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A
|
||||
technology.sky130.sram22_sky130_macros: ~/sram22_sky130_macros
|
||||
|
||||
example-openroad.yml
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
This contains the Hammer configuration for the OpenROAD tool flow.
|
||||
It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen).
|
||||
|
||||
Add the following YAML keys to the top of this file to specify the locations of the tool binaries.
|
||||
Note that this is not required if the tools are already on your PATH.
|
||||
|
||||
.. code-block:: yaml
|
||||
|
||||
# all ~ should be replaced with absolute paths to these directories
|
||||
# tool binary paths
|
||||
synthesis.yosys.yosys_bin: ~/.conda-yosys/bin/yosys
|
||||
par.openroad.openroad_bin: ~/.conda-openroad/bin/openroad
|
||||
par.openroad.klayout_bin: ~/.conda-klayout/bin/klayout
|
||||
drc.magic.magic_bin: ~/.conda-signoff/bin/magic
|
||||
lvs.netgen.netgen_bin: ~/.conda-signoff/bin/netgen
|
||||
|
||||
|
||||
Building the Design
|
||||
--------------------
|
||||
|
||||
To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make buildfile tutorial=sky130-openroad
|
||||
|
||||
The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
|
||||
It needs to be re-run if environment variables are changed.
|
||||
It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
|
||||
|
||||
The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources
|
||||
and (2) the mapping of memory instances in the design to SRAM macros;
|
||||
all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory.
|
||||
Note that the files in ``generated-src`` vary for each tool/technology flow.
|
||||
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
|
||||
(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
|
||||
chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
|
||||
|
||||
|
||||
For the sake of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``,
|
||||
which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
|
||||
|
||||
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
|
||||
* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
|
||||
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described above
|
||||
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
|
||||
* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
|
||||
* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
|
||||
* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
|
||||
|
||||
Running the VLSI Flow
|
||||
---------------------
|
||||
|
||||
Synthesis
|
||||
^^^^^^^^^
|
||||
|
||||
@@ -128,38 +187,79 @@ Place-and-Route
|
||||
|
||||
make par tutorial=sky130-openroad
|
||||
|
||||
Note that sometimes OpenROAD freezes on commands following the ``detailed_route`` step,
|
||||
so for now we recomment running place-and-route until the ``extraction`` step,
|
||||
then re-starting the flow at this step. See the :ref:`VLSI/Sky130-OpenROAD-Tutorial:VLSI Flow Control` documentation
|
||||
below for how to break up the flow into these steps.
|
||||
|
||||
After completion, the final database can be opened in an interactive OpenROAD session.
|
||||
Hammer generates a convenient script to launch these sessions
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
cd ./build/par-rundir
|
||||
cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
|
||||
./generated-scripts/open_chip
|
||||
|
||||
Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout,
|
||||
you will need to install OpenROAD from source.
|
||||
|
||||
Below is the post-PnR layout for the TinyRocketConfig in Sky130 generated by OpenROAD.
|
||||
|
||||
.. image:: ../_static/images/vlsi-openroad-par-tinyrocketconfig.png
|
||||
|
||||
Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action. These databases can be restored in an interactive OpenROAD session as desired for debugging purposes.
|
||||
Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action,
|
||||
These databases can be restored using the same ``open_chip`` script for debugging purposes.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
openroad # launch OpenROAD tool
|
||||
openroad> read_db pre_global_route
|
||||
cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
|
||||
./generated_scripts/open_chip -h
|
||||
"
|
||||
Usage: ./generated-scripts/open_chip [-t] [openroad_db_name]
|
||||
|
||||
.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
|
||||
Options
|
||||
openroad_db_name : Name of database to load (default=latest)
|
||||
-t, --timing : Load timing info (default=disabled because of slow load time)
|
||||
-h, --help : Display this message
|
||||
"
|
||||
# load pre-global route database without timing information
|
||||
./generated_scripts/open_chip pre_global_route
|
||||
|
||||
# load post-clock tree database with timing inforamtion
|
||||
./generated_scripts/open_chip -t post_clock_tree
|
||||
|
||||
Various reports, including timing reports, are found in ``build/par-rundir/reports``.
|
||||
|
||||
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
|
||||
|
||||
DRC & LVS
|
||||
^^^^^^^^^
|
||||
To run DRC & LVS:
|
||||
|
||||
As a note, this tutorial has been run extensively through commercial signoff tools,
|
||||
thus the open-source signoff flow is not stable or guaranteed to produce useful results.
|
||||
We welcome any contributions to improving both our `Magic tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/drc/magic>`__
|
||||
and `Netgen tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/lvs/netgen>`__.
|
||||
|
||||
To run DRC & LVS in Magic & Netgen, respectively:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make drc tutorial=sky130-openroad
|
||||
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
|
||||
make lvs tutorial=sky130-openroad
|
||||
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
|
||||
|
||||
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
|
||||
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.
|
||||
Note that in ``sky130-openroad.yml`` we have set the following YAML keys:
|
||||
|
||||
.. code-block:: yaml
|
||||
|
||||
drc.magic.generate_only: true
|
||||
lvs.netgen.generate_only: true
|
||||
|
||||
These keys cause the Hammer plugin to only generate all necessary scripts, without executing them with the respective tool.
|
||||
This is because Magic and Netgen, as of the writing of this tutorial, do not have a database format that may be loaded interactively,
|
||||
so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks,
|
||||
which is done by the ``generated-scripts/view_[drc|lvs]`` scripts.
|
||||
|
||||
|
||||
VLSI Flow Control
|
||||
@@ -168,15 +268,20 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
# the following two statements are equivalent because the
|
||||
# extraction step immediately precedes the write_design step
|
||||
# the following two commands run the entire flow, using the pre_extraction
|
||||
# database to save and reload a checkpoint of the design
|
||||
make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
|
||||
make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
|
||||
|
||||
# the following two commands are equivalent because the extraction
|
||||
# step immediately precedes the write_design step
|
||||
make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
|
||||
make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"
|
||||
|
||||
# example of re-running only floorplanning to test out a new floorplan configuration
|
||||
make redo-par HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-sky130.yml"
|
||||
|
||||
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
|
||||
# the "-p file.yml" causes file.yml to override any previous yaml/json configurations
|
||||
make redo-par \
|
||||
HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-designs/sky130-openroad.yml"
|
||||
|
||||
Documentation
|
||||
-------------
|
||||
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 1.9 MiB After Width: | Height: | Size: 1.6 MiB |
Submodule generators/boom updated: deae9f7046...051dbadb6d
@@ -70,7 +70,7 @@ extern "C" void cospike_cosim(long long int cycle,
|
||||
if (!sim) {
|
||||
printf("Configuring spike cosim\n");
|
||||
std::vector<mem_cfg_t> mem_cfg;
|
||||
std::vector<int> hartids;
|
||||
std::vector<size_t> hartids;
|
||||
mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size));
|
||||
for (int i = 0; i < info->nharts; i++)
|
||||
hartids.push_back(i);
|
||||
|
||||
@@ -6,6 +6,9 @@
|
||||
#include <sstream>
|
||||
#include <vpi_user.h>
|
||||
#include <svdpi.h>
|
||||
#include "testchip_tsi.h"
|
||||
|
||||
extern testchip_tsi_t* tsi;
|
||||
|
||||
enum transfer_t {
|
||||
NToB,
|
||||
@@ -73,9 +76,18 @@ public:
|
||||
void dcache_b(uint64_t address, uint64_t source, int param);
|
||||
bool dcache_c(uint64_t *address, uint64_t* source, int* param, unsigned char* voluntary, unsigned char* has_data, uint64_t* data[8]);
|
||||
void dcache_d(uint64_t sourceid, uint64_t data[8], unsigned char has_data, unsigned char grantack);
|
||||
|
||||
void tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size);
|
||||
bool tcm_d(uint64_t *data);
|
||||
|
||||
void loadmem(const char* fname);
|
||||
|
||||
void drain_stq();
|
||||
bool stq_empty() { return st_q.size() == 0; };
|
||||
|
||||
|
||||
const cfg_t &get_cfg() const { return cfg; }
|
||||
const std::map<size_t, processor_t*>& get_harts() const { return harts; }
|
||||
|
||||
~chipyard_simif_t() { };
|
||||
chipyard_simif_t(size_t icache_ways,
|
||||
size_t icache_sets,
|
||||
@@ -86,9 +98,17 @@ public:
|
||||
char* readonly_uncacheable,
|
||||
char* executable,
|
||||
size_t icache_sourceids,
|
||||
size_t dcache_sourceids);
|
||||
size_t dcache_sourceids,
|
||||
size_t tcm_base,
|
||||
size_t tcm_size,
|
||||
const char* isastr,
|
||||
size_t pmpregions);
|
||||
uint64_t cycle;
|
||||
bool use_stq;
|
||||
htif_t *htif;
|
||||
bool fast_clint;
|
||||
cfg_t cfg;
|
||||
std::map<size_t, processor_t*> harts;
|
||||
private:
|
||||
bool handle_cache_access(reg_t addr, size_t len,
|
||||
uint8_t* load_bytes,
|
||||
@@ -133,6 +153,11 @@ private:
|
||||
uint64_t mmio_stdata;
|
||||
size_t mmio_len;
|
||||
uint64_t mmio_lddata;
|
||||
|
||||
uint64_t tcm_base;
|
||||
uint64_t tcm_size;
|
||||
uint8_t* tcm;
|
||||
std::vector<uint64_t> tcm_q;
|
||||
};
|
||||
|
||||
class tile_t {
|
||||
@@ -163,6 +188,7 @@ extern "C" void spike_tile(int hartid, char* isa,
|
||||
int dcache_sets, int dcache_ways,
|
||||
char* cacheable, char* uncacheable, char* readonly_uncacheable, char* executable,
|
||||
int icache_sourceids, int dcache_sourceids,
|
||||
long long int tcm_base, long long int tcm_size,
|
||||
long long int reset_vector,
|
||||
long long int ipc,
|
||||
long long int cycle,
|
||||
@@ -237,7 +263,18 @@ extern "C" void spike_tile(int hartid, char* isa,
|
||||
int* mmio_a_size,
|
||||
|
||||
unsigned char mmio_d_valid,
|
||||
long long int mmio_d_data
|
||||
long long int mmio_d_data,
|
||||
|
||||
unsigned char tcm_a_valid,
|
||||
long long int tcm_a_address,
|
||||
long long int tcm_a_data,
|
||||
int tcm_a_mask,
|
||||
int tcm_a_opcode,
|
||||
int tcm_a_size,
|
||||
|
||||
unsigned char* tcm_d_valid,
|
||||
unsigned char tcm_d_ready,
|
||||
long long int* tcm_d_data
|
||||
)
|
||||
{
|
||||
if (!host) {
|
||||
@@ -248,36 +285,26 @@ extern "C" void spike_tile(int hartid, char* isa,
|
||||
if (tiles.find(hartid) == tiles.end()) {
|
||||
printf("Constructing spike processor_t\n");
|
||||
isa_parser_t *isa_parser = new isa_parser_t(isa, "MSU");
|
||||
std::string* isastr = new std::string(isa);
|
||||
chipyard_simif_t* simif = new chipyard_simif_t(icache_ways, icache_sets,
|
||||
dcache_ways, dcache_sets,
|
||||
cacheable, uncacheable, readonly_uncacheable, executable,
|
||||
icache_sourceids, dcache_sourceids);
|
||||
std::string* isastr = new std::string(isa);
|
||||
cfg_t* cfg = new cfg_t(std::make_pair(0, 0),
|
||||
nullptr,
|
||||
isastr->c_str(),
|
||||
"MSU",
|
||||
"vlen:128,elen:64",
|
||||
false,
|
||||
endianness_little,
|
||||
pmpregions,
|
||||
std::vector<mem_cfg_t>(),
|
||||
std::vector<int>(),
|
||||
false,
|
||||
0);
|
||||
icache_sourceids, dcache_sourceids,
|
||||
tcm_base, tcm_size,
|
||||
isastr->c_str(), pmpregions);
|
||||
processor_t* p = new processor_t(isa_parser,
|
||||
cfg,
|
||||
&simif->get_cfg(),
|
||||
simif,
|
||||
hartid,
|
||||
false,
|
||||
log_file->get(),
|
||||
sout);
|
||||
|
||||
p->enable_log_commits();
|
||||
simif->harts[hartid] = p;
|
||||
|
||||
s_vpi_vlog_info vinfo;
|
||||
if (!vpi_get_vlog_info(&vinfo))
|
||||
abort();
|
||||
std::string loadmem_file = "";
|
||||
for (int i = 1; i < vinfo.argc; i++) {
|
||||
std::string arg(vinfo.argv[i]);
|
||||
if (arg == "+spike-debug") {
|
||||
@@ -286,7 +313,18 @@ extern "C" void spike_tile(int hartid, char* isa,
|
||||
if (arg == "+spike-stq") {
|
||||
simif->use_stq = true;
|
||||
}
|
||||
if (arg.find("+loadmem=") == 0) {
|
||||
loadmem_file = arg.substr(strlen("+loadmem="));
|
||||
}
|
||||
if (arg == "+spike-fast-clint") {
|
||||
simif->fast_clint = true;
|
||||
}
|
||||
if (arg == "+spike-verbose") {
|
||||
p->enable_log_commits();
|
||||
}
|
||||
}
|
||||
if (loadmem_file != "" && tcm_size > 0)
|
||||
simif->loadmem(loadmem_file.c_str());
|
||||
|
||||
p->reset();
|
||||
p->get_state()->pc = reset_vector;
|
||||
@@ -296,6 +334,9 @@ extern "C" void spike_tile(int hartid, char* isa,
|
||||
tile_t* tile = tiles[hartid];
|
||||
chipyard_simif_t* simif = tile->simif;
|
||||
processor_t* proc = tile->proc;
|
||||
if (!simif->htif && tsi) {
|
||||
simif->htif = (htif_t*) tsi;
|
||||
}
|
||||
|
||||
simif->cycle = cycle;
|
||||
if (debug) {
|
||||
@@ -357,6 +398,13 @@ extern "C" void spike_tile(int hartid, char* isa,
|
||||
if (mmio_d_valid) {
|
||||
simif->mmio_d(mmio_d_data);
|
||||
}
|
||||
|
||||
if (tcm_a_valid) {
|
||||
simif->tcm_a(tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size);
|
||||
}
|
||||
if (tcm_d_ready) {
|
||||
*tcm_d_valid = simif->tcm_d((uint64_t*)tcm_d_data);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -369,14 +417,34 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways,
|
||||
char* readonly_uncacheable,
|
||||
char* executable,
|
||||
size_t ic_sourceids,
|
||||
size_t dc_sourceids
|
||||
size_t dc_sourceids,
|
||||
size_t tcm_base,
|
||||
size_t tcm_size,
|
||||
const char* isastr,
|
||||
size_t pmpregions
|
||||
) :
|
||||
cycle(0),
|
||||
use_stq(false),
|
||||
htif(nullptr),
|
||||
fast_clint(false),
|
||||
cfg(std::make_pair(0, 0),
|
||||
nullptr,
|
||||
isastr,
|
||||
"MSU",
|
||||
"vlen:128,elen:64",
|
||||
false,
|
||||
endianness_little,
|
||||
pmpregions,
|
||||
std::vector<mem_cfg_t>(),
|
||||
std::vector<size_t>(),
|
||||
false,
|
||||
0),
|
||||
icache_ways(icache_ways),
|
||||
icache_sets(icache_sets),
|
||||
dcache_ways(dcache_ways),
|
||||
dcache_sets(dcache_sets),
|
||||
tcm_base(tcm_base),
|
||||
tcm_size(tcm_size),
|
||||
mmio_valid(false),
|
||||
mmio_inflight(false)
|
||||
{
|
||||
@@ -432,6 +500,8 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways,
|
||||
uint64_t size_int = std::stoul(size);
|
||||
executables.push_back(mem_region_t { base_int, size_int });
|
||||
}
|
||||
|
||||
tcm = (uint8_t*)malloc(tcm_size);
|
||||
}
|
||||
|
||||
bool chipyard_simif_t::reservable(reg_t addr) {
|
||||
@@ -440,12 +510,20 @@ bool chipyard_simif_t::reservable(reg_t addr) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
if (addr >= tcm_base && addr < tcm_base + tcm_size) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool chipyard_simif_t::mmio_fetch(reg_t addr, size_t len, uint8_t* bytes) {
|
||||
bool executable = false;
|
||||
|
||||
if (addr >= tcm_base && addr < tcm_base + tcm_size) {
|
||||
memcpy(bytes, tcm + addr - tcm_base, len);
|
||||
return true;
|
||||
}
|
||||
|
||||
for (auto& r: executables) {
|
||||
if (addr >= r.base && addr + len <= r.base + r.size) {
|
||||
executable = true;
|
||||
@@ -466,6 +544,10 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) {
|
||||
bool found = false;
|
||||
bool cacheable = false;
|
||||
bool readonly = false;
|
||||
if (addr >= tcm_base && addr < tcm_base + tcm_size) {
|
||||
memcpy(bytes, tcm + addr - tcm_base, len);
|
||||
return true;
|
||||
}
|
||||
for (auto& r: cacheables) {
|
||||
if (addr >= r.base && addr + len <= r.base + r.size) {
|
||||
cacheable = true;
|
||||
@@ -488,7 +570,7 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (!found) {
|
||||
return false;
|
||||
}
|
||||
@@ -576,7 +658,7 @@ bool chipyard_simif_t::handle_cache_access(reg_t addr, size_t len,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define SETIDX(ADDR) ((ADDR >> 6) & (n_sets - 1))
|
||||
uint64_t setidx = SETIDX(addr);
|
||||
uint64_t offset = addr & (64 - 1);
|
||||
@@ -829,9 +911,14 @@ bool chipyard_simif_t::dcache_c(uint64_t* address, uint64_t* source, int* param,
|
||||
}
|
||||
|
||||
bool chipyard_simif_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) {
|
||||
if (addr >= tcm_base && addr < tcm_base + tcm_size) {
|
||||
memcpy(tcm + addr - tcm_base, bytes, len);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool found = false;
|
||||
bool cacheable = false;
|
||||
for (auto& r: cacheables) {
|
||||
for (auto& r: cacheables) {
|
||||
if (addr >= r.base && addr + len <= r.base + r.size) {
|
||||
cacheable = true;
|
||||
found = true;
|
||||
@@ -899,27 +986,108 @@ void chipyard_simif_t::dcache_d(uint64_t sourceid, uint64_t data[8], unsigned ch
|
||||
}
|
||||
}
|
||||
|
||||
void chipyard_simif_t::tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size) {
|
||||
bool load = opcode == 4;
|
||||
uint64_t rdata = 0;
|
||||
memcpy(&rdata, tcm + address - tcm_base, 8);
|
||||
tcm_q.push_back(rdata);
|
||||
|
||||
if (!load) {
|
||||
for (size_t i = 0; i < 8; i++) {
|
||||
if ((mask >> i) & 1) {
|
||||
memcpy(tcm + address - tcm_base + i, ((uint8_t*)&data) + i, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool chipyard_simif_t::tcm_d(uint64_t* data) {
|
||||
if (tcm_q.size() == 0)
|
||||
return false;
|
||||
*data = tcm_q[0];
|
||||
tcm_q.erase(tcm_q.begin());
|
||||
return true;
|
||||
}
|
||||
|
||||
#define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0')
|
||||
void chipyard_simif_t::loadmem(const char* fname) {
|
||||
std::ifstream in(fname);
|
||||
std::string line;
|
||||
if (!in.is_open()) {
|
||||
printf("SpikeTile couldn't open loadmem file %s\n", fname);
|
||||
abort();
|
||||
}
|
||||
size_t fsize = 0;
|
||||
size_t start = 0;
|
||||
while (std::getline(in, line)) {
|
||||
for (ssize_t i = line.length()-2, j = 0; i >= 0; i -= 2, j++) {
|
||||
char byte = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]);
|
||||
ssize_t addr = (start + j) % tcm_size;
|
||||
tcm[addr] = (uint8_t)byte;
|
||||
}
|
||||
start += line.length()/2;
|
||||
fsize += line.length()/2;
|
||||
|
||||
if (fsize > tcm_size) {
|
||||
fprintf(stderr, "Loadmem file is too large\n");
|
||||
abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool insn_should_fence(uint64_t bits) {
|
||||
uint8_t opcode = bits & 0x7f;
|
||||
return opcode == 0b0101111 || opcode == 0b0001111;
|
||||
}
|
||||
|
||||
bool insn_is_wfi(uint64_t bits) {
|
||||
return bits == 0x10500073;
|
||||
}
|
||||
|
||||
void spike_thread_main(void* arg)
|
||||
{
|
||||
tile_t* tile = (tile_t*) arg;
|
||||
processor_t* proc = tile->proc;
|
||||
chipyard_simif_t* simif = tile->simif;
|
||||
state_t* state = proc->get_state();
|
||||
while (true) {
|
||||
while (tile->max_insns == 0) {
|
||||
host->switch_to();
|
||||
}
|
||||
while (tile->max_insns != 0) {
|
||||
// TODO: Fences don't work
|
||||
// uint64_t last_bits = tile->proc->get_last_bits();
|
||||
// if (insn_should_fence(last_bits) && !tile->simif->stq_empty()) {
|
||||
//uint64_t last_bits = proc->get_last_bits();
|
||||
// if (insn_should_fence(last_bits) && !simif->stq_empty()) {
|
||||
// host->switch_to();
|
||||
// }
|
||||
tile->proc->step(1);
|
||||
proc->step(1);
|
||||
tile->max_insns--;
|
||||
tile->proc->get_state()->mcycle->write(tile->simif->cycle);
|
||||
if (proc->is_waiting_for_interrupt()) {
|
||||
if (simif->fast_clint) {
|
||||
// uint64_t mip = state->mip->read();
|
||||
// uint64_t mie = state->mie->read();
|
||||
//printf("Setting MTIP %x %x %x %x %lx\n", simif->cycle, old_minstret, mip, mie,
|
||||
// state->pc);
|
||||
state->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP);
|
||||
tile->max_insns = tile->max_insns <= 1 ? 0 : 1;
|
||||
} else {
|
||||
//printf("SpikeTile in WFI\n");
|
||||
tile->max_insns = 0;
|
||||
}
|
||||
}
|
||||
if (tile->max_insns % 100 == 0) {
|
||||
uint64_t old_minstret = state->minstret->read();
|
||||
uint64_t tohost_addr = simif->htif ? simif->htif->get_tohost_addr() : 0;
|
||||
uint64_t fromhost_addr = simif->htif ? simif->htif->get_fromhost_addr() : 0;
|
||||
auto& mem_read = state->log_mem_read;
|
||||
reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]);
|
||||
if ((old_minstret == state->minstret->read()) ||
|
||||
(tohost_addr && mem_read_addr == tohost_addr) ||
|
||||
(fromhost_addr && mem_read_addr == fromhost_addr)) {
|
||||
tile->max_insns == 0;
|
||||
}
|
||||
}
|
||||
state->mcycle->write(simif->cycle);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -13,6 +13,8 @@ import "DPI-C" function void spike_tile(input int hartid,
|
||||
input string executable,
|
||||
input int icache_sourceids,
|
||||
input int dcache_sourceids,
|
||||
input longint tcm_base,
|
||||
input longint tcm_size,
|
||||
input longint reset_vector,
|
||||
input longint ipc,
|
||||
input longint cycle,
|
||||
@@ -89,7 +91,18 @@ import "DPI-C" function void spike_tile(input int hartid,
|
||||
output int mmio_a_size,
|
||||
|
||||
input bit mmio_d_valid,
|
||||
input longint mmio_d_data
|
||||
input longint mmio_d_data,
|
||||
|
||||
input bit tcm_a_valid,
|
||||
input longint tcm_a_address,
|
||||
input longint tcm_a_data,
|
||||
input int tcm_a_mask,
|
||||
input int tcm_a_opcode,
|
||||
input int tcm_a_size,
|
||||
|
||||
output bit tcm_d_valid,
|
||||
input bit tcm_d_ready,
|
||||
output longint tcm_d_data
|
||||
);
|
||||
|
||||
|
||||
@@ -106,7 +119,9 @@ module SpikeBlackBox #(
|
||||
parameter READONLY_UNCACHEABLE,
|
||||
parameter EXECUTABLE,
|
||||
parameter ICACHE_SOURCEIDS,
|
||||
parameter DCACHE_SOURCEIDS )(
|
||||
parameter DCACHE_SOURCEIDS,
|
||||
parameter TCM_BASE,
|
||||
parameter TCM_SIZE)(
|
||||
input clock,
|
||||
input reset,
|
||||
input [63:0] reset_vector,
|
||||
@@ -185,7 +200,18 @@ module SpikeBlackBox #(
|
||||
output [31:0] mmio_a_size,
|
||||
|
||||
input mmio_d_valid,
|
||||
input [63:0] mmio_d_data
|
||||
input [63:0] mmio_d_data,
|
||||
|
||||
input tcm_a_valid,
|
||||
input [63:0] tcm_a_address,
|
||||
input [63:0] tcm_a_data,
|
||||
input [31:0] tcm_a_mask,
|
||||
input [31:0] tcm_a_opcode,
|
||||
input [31:0] tcm_a_size,
|
||||
|
||||
output tcm_d_valid,
|
||||
input tcm_d_ready,
|
||||
output [63:0] tcm_d_data
|
||||
);
|
||||
|
||||
longint __insns_retired;
|
||||
@@ -257,7 +283,13 @@ module SpikeBlackBox #(
|
||||
reg [63:0] __dcache_c_data_6_reg;
|
||||
reg [63:0] __dcache_c_data_7_reg;
|
||||
|
||||
|
||||
wire __tcm_d_ready;
|
||||
bit __tcm_d_valid;
|
||||
longint __tcm_d_data;
|
||||
|
||||
reg __tcm_d_valid_reg;
|
||||
reg [63:0] __tcm_d_data_reg;
|
||||
|
||||
|
||||
|
||||
always @(posedge clock) begin
|
||||
@@ -322,12 +354,18 @@ module SpikeBlackBox #(
|
||||
__dcache_c_data_6_reg <= 64'h0;
|
||||
__dcache_c_data_7 = 64'h0;
|
||||
__dcache_c_data_7_reg <= 64'h0;
|
||||
|
||||
__tcm_d_valid = 1'b0;
|
||||
__tcm_d_valid_reg <= 1'b0;
|
||||
__tcm_d_data = 64'h0;
|
||||
__tcm_d_data_reg <= 64'h0;
|
||||
spike_tile_reset(HARTID);
|
||||
end else begin
|
||||
spike_tile(HARTID, ISA, PMPREGIONS,
|
||||
ICACHE_SETS, ICACHE_WAYS, DCACHE_SETS, DCACHE_WAYS,
|
||||
CACHEABLE, UNCACHEABLE, READONLY_UNCACHEABLE, EXECUTABLE,
|
||||
ICACHE_SOURCEIDS, DCACHE_SOURCEIDS,
|
||||
TCM_BASE, TCM_SIZE,
|
||||
reset_vector, ipc, cycle, __insns_retired,
|
||||
debug, mtip, msip, meip, seip,
|
||||
|
||||
@@ -350,7 +388,10 @@ module SpikeBlackBox #(
|
||||
dcache_d_data_4, dcache_d_data_5, dcache_d_data_6, dcache_d_data_7,
|
||||
|
||||
__mmio_a_ready, __mmio_a_valid, __mmio_a_address, __mmio_a_data, __mmio_a_store, __mmio_a_size,
|
||||
mmio_d_valid, mmio_d_data
|
||||
mmio_d_valid, mmio_d_data,
|
||||
|
||||
tcm_a_valid, tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size,
|
||||
__tcm_d_valid, __tcm_d_ready, __tcm_d_data
|
||||
);
|
||||
__insns_retired_reg <= __insns_retired;
|
||||
|
||||
@@ -385,6 +426,10 @@ module SpikeBlackBox #(
|
||||
__mmio_a_data_reg <= __mmio_a_data;
|
||||
__mmio_a_store_reg <= __mmio_a_store;
|
||||
__mmio_a_size_reg <= __mmio_a_size;
|
||||
|
||||
__tcm_d_valid_reg <= __tcm_d_valid;
|
||||
__tcm_d_data_reg <= __tcm_d_data;
|
||||
|
||||
end
|
||||
end // always @ (posedge clock)
|
||||
assign insns_retired = __insns_retired_reg;
|
||||
@@ -424,6 +469,8 @@ module SpikeBlackBox #(
|
||||
assign mmio_a_size = __mmio_a_size_reg;
|
||||
assign __mmio_a_ready = mmio_a_ready;
|
||||
|
||||
|
||||
assign tcm_d_valid = __tcm_d_valid_reg;
|
||||
assign tcm_d_data = __tcm_d_data_reg;
|
||||
assign __tcm_d_ready = tcm_d_ready;
|
||||
|
||||
endmodule;
|
||||
|
||||
@@ -51,6 +51,12 @@ case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
|
||||
Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
|
||||
)
|
||||
|
||||
case object DontTouchIOBindersPorts extends Field[Boolean](true)
|
||||
|
||||
class WithDontTouchIOBinders(b: Boolean = true) extends Config((site, here, up) => {
|
||||
case DontTouchIOBindersPorts => b
|
||||
})
|
||||
|
||||
abstract trait HasIOBinders { this: LazyModule =>
|
||||
val lazySystem: LazyModule
|
||||
private val iobinders = p(IOBinders)
|
||||
@@ -67,10 +73,33 @@ abstract trait HasIOBinders { this: LazyModule =>
|
||||
})
|
||||
|
||||
// A publicly accessible list of IO cells (useful for a floorplanning tool, for example)
|
||||
lazy val iocells = (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer
|
||||
val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer }
|
||||
|
||||
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports
|
||||
lazy val portMap = iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap
|
||||
val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap }
|
||||
|
||||
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
|
||||
val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }
|
||||
|
||||
InModuleBody {
|
||||
if (p(DontTouchIOBindersPorts)) {
|
||||
portMap.values.foreach(_.foreach(dontTouch(_)))
|
||||
}
|
||||
|
||||
println("IOCells generated by IOBinders:")
|
||||
for ((k, v) <- iocellMap) {
|
||||
if (!v.isEmpty) {
|
||||
val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
|
||||
|
||||
println(s" IOBinder for $k generated:")
|
||||
for ((t, c) <- cells) { println(s" $c X $t") }
|
||||
}
|
||||
}
|
||||
println()
|
||||
val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
|
||||
println(s" Total generated ${iocells.size} IOCells:")
|
||||
for ((t, c) <- totals) { println(s" $c X $t") }
|
||||
}
|
||||
}
|
||||
|
||||
// Note: The parameters instance is accessible only through LazyModule
|
||||
|
||||
@@ -15,8 +15,7 @@ import freechips.rocketchip.util._
|
||||
import freechips.rocketchip.tile._
|
||||
import freechips.rocketchip.prci.ClockSinkParameters
|
||||
|
||||
case class SpikeCoreParams(
|
||||
) extends CoreParams {
|
||||
case class SpikeCoreParams() extends CoreParams {
|
||||
val useVM = true
|
||||
val useHypervisor = false
|
||||
val useSupervisor = true
|
||||
@@ -79,7 +78,8 @@ case class SpikeTileParams(
|
||||
hartId: Int = 0,
|
||||
val core: SpikeCoreParams = SpikeCoreParams(),
|
||||
icacheParams: ICacheParams = ICacheParams(nWays = 32),
|
||||
dcacheParams: DCacheParams = DCacheParams(nWays = 32)
|
||||
dcacheParams: DCacheParams = DCacheParams(nWays = 32),
|
||||
tcmParams: Option[MasterPortParams] = None // tightly coupled memory
|
||||
) extends InstantiableTileParams[SpikeTile]
|
||||
{
|
||||
val name = Some("spike_tile")
|
||||
@@ -145,6 +145,27 @@ class SpikeTile(
|
||||
sourceId = IdRange(0, 1),
|
||||
requestFifo = true))))))
|
||||
|
||||
tlSlaveXbar.node :*= slaveNode
|
||||
val tcmNode = spikeTileParams.tcmParams.map { tcmP =>
|
||||
val device = new MemoryDevice
|
||||
val base = AddressSet.misaligned(tcmP.base, tcmP.size)
|
||||
val tcmNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
|
||||
managers = Seq(TLSlaveParameters.v1(
|
||||
address = base,
|
||||
resources = device.reg,
|
||||
regionType = RegionType.IDEMPOTENT, // not cacheable
|
||||
executable = true,
|
||||
supportsGet = TransferSizes(1, 8),
|
||||
supportsPutFull = TransferSizes(1, 8),
|
||||
supportsPutPartial = TransferSizes(1, 8),
|
||||
fifoId = Some(0)
|
||||
)),
|
||||
beatBytes = 8
|
||||
)))
|
||||
connectTLSlave(tcmNode := TLBuffer(), 8)
|
||||
tcmNode
|
||||
}
|
||||
|
||||
tlOtherMastersNode := TLBuffer() := tlMasterXbar.node
|
||||
masterNode :=* tlOtherMastersNode
|
||||
tlMasterXbar.node := TLWidthWidget(64) := TLBuffer():= icacheNode
|
||||
@@ -166,7 +187,9 @@ class SpikeBlackBox(
|
||||
cacheable_regions: String,
|
||||
uncacheable_regions: String,
|
||||
readonly_uncacheable_regions: String,
|
||||
executable_regions: String) extends BlackBox(Map(
|
||||
executable_regions: String,
|
||||
tcm_base: BigInt,
|
||||
tcm_size: BigInt) extends BlackBox(Map(
|
||||
"HARTID" -> IntParam(hartId),
|
||||
"ISA" -> StringParam(isa),
|
||||
"PMPREGIONS" -> IntParam(pmpregions),
|
||||
@@ -179,7 +202,9 @@ class SpikeBlackBox(
|
||||
"UNCACHEABLE" -> StringParam(uncacheable_regions),
|
||||
"READONLY_UNCACHEABLE" -> StringParam(readonly_uncacheable_regions),
|
||||
"CACHEABLE" -> StringParam(cacheable_regions),
|
||||
"EXECUTABLE" -> StringParam(executable_regions)
|
||||
"EXECUTABLE" -> StringParam(executable_regions),
|
||||
"TCM_BASE" -> IntParam(tcm_base),
|
||||
"TCM_SIZE" -> IntParam(tcm_size)
|
||||
)) with HasBlackBoxResource {
|
||||
|
||||
val io = IO(new Bundle {
|
||||
@@ -258,6 +283,22 @@ class SpikeBlackBox(
|
||||
val data = Input(UInt(64.W))
|
||||
}
|
||||
}
|
||||
|
||||
val tcm = new Bundle {
|
||||
val a = new Bundle {
|
||||
val valid = Input(Bool())
|
||||
val address = Input(UInt(64.W))
|
||||
val data = Input(UInt(64.W))
|
||||
val mask = Input(UInt(32.W))
|
||||
val opcode = Input(UInt(32.W))
|
||||
val size = Input(UInt(32.W))
|
||||
}
|
||||
val d = new Bundle {
|
||||
val valid = Output(Bool())
|
||||
val ready = Input(Bool())
|
||||
val data = Output(UInt(64.W))
|
||||
}
|
||||
}
|
||||
})
|
||||
addResource("/vsrc/spiketile.v")
|
||||
addResource("/csrc/spiketile.cc")
|
||||
@@ -289,7 +330,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
|
||||
tileParams.icache.get.nSets, tileParams.icache.get.nWays,
|
||||
tileParams.dcache.get.nSets, tileParams.dcache.get.nWays,
|
||||
tileParams.dcache.get.nMSHRs,
|
||||
cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions))
|
||||
cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions,
|
||||
outer.spikeTileParams.tcmParams.map(_.base).getOrElse(0),
|
||||
outer.spikeTileParams.tcmParams.map(_.size).getOrElse(0)
|
||||
))
|
||||
spike.io.clock := clock.asBool
|
||||
val cycle = RegInit(0.U(64.W))
|
||||
cycle := cycle + 1.U
|
||||
@@ -304,64 +348,63 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
|
||||
spike.io.msip := int_bundle.msip
|
||||
spike.io.meip := int_bundle.meip
|
||||
spike.io.seip := int_bundle.seip.get
|
||||
spike.io.ipc := PlusArg("spike-ipc", 10000, width=64)
|
||||
spike.io.ipc := PlusArg("spike-ipc", width=32, default=10000)
|
||||
|
||||
val blockBits = log2Ceil(p(CacheBlockBytes))
|
||||
|
||||
val icache_a_q = Module(new Queue(new TLBundleA(icacheEdge.bundle), 1, flow=true, pipe=true))
|
||||
spike.io.icache.a.ready := icache_a_q.io.enq.ready && icache_a_q.io.count === 0.U
|
||||
icache_tl.a <> icache_a_q.io.deq
|
||||
icache_a_q.io.enq.valid := spike.io.icache.a.valid
|
||||
icache_a_q.io.enq.bits := icacheEdge.Get(
|
||||
spike.io.icache.a.ready := icache_tl.a.ready
|
||||
icache_tl.a.valid := spike.io.icache.a.valid
|
||||
icache_tl.a.bits := icacheEdge.Get(
|
||||
fromSource = spike.io.icache.a.sourceid,
|
||||
toAddress = (spike.io.icache.a.address >> blockBits) << blockBits,
|
||||
lgSize = blockBits.U)._2
|
||||
|
||||
icache_tl.d.ready := true.B
|
||||
spike.io.icache.d.valid := icache_tl.d.valid
|
||||
spike.io.icache.d.sourceid := icache_tl.d.bits.source
|
||||
spike.io.icache.d.data := icache_tl.d.bits.data.asTypeOf(Vec(8, UInt(64.W)))
|
||||
|
||||
val dcache_a_q = Module(new Queue(new TLBundleA(dcacheEdge.bundle), 1, flow=true, pipe=true))
|
||||
spike.io.dcache.a.ready := dcache_a_q.io.enq.ready && dcache_a_q.io.count === 0.U
|
||||
dcache_tl.a <> dcache_a_q.io.deq
|
||||
dcache_a_q.io.enq.valid := spike.io.dcache.a.valid
|
||||
dcache_a_q.io.enq.bits := dcacheEdge.AcquireBlock(
|
||||
fromSource = spike.io.dcache.a.sourceid,
|
||||
toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits,
|
||||
lgSize = blockBits.U,
|
||||
growPermissions = Mux(spike.io.dcache.a.state_old, 2.U, Mux(spike.io.dcache.a.state_new, 1.U, 0.U)))._2
|
||||
|
||||
spike.io.dcache.a.ready := dcache_tl.a.ready
|
||||
dcache_tl.a.valid := spike.io.dcache.a.valid
|
||||
if (dcacheEdge.manager.anySupportAcquireB) {
|
||||
dcache_tl.a.bits := dcacheEdge.AcquireBlock(
|
||||
fromSource = spike.io.dcache.a.sourceid,
|
||||
toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits,
|
||||
lgSize = blockBits.U,
|
||||
growPermissions = Mux(spike.io.dcache.a.state_old, 2.U, Mux(spike.io.dcache.a.state_new, 1.U, 0.U)))._2
|
||||
} else {
|
||||
dcache_tl.a.bits := DontCare
|
||||
}
|
||||
dcache_tl.b.ready := true.B
|
||||
spike.io.dcache.b.valid := dcache_tl.b.valid
|
||||
spike.io.dcache.b.address := dcache_tl.b.bits.address
|
||||
spike.io.dcache.b.source := dcache_tl.b.bits.source
|
||||
spike.io.dcache.b.param := dcache_tl.b.bits.param
|
||||
|
||||
val dcache_c_q = Module(new Queue(new TLBundleC(dcacheEdge.bundle), 1, flow=true, pipe=true))
|
||||
spike.io.dcache.c.ready := dcache_c_q.io.enq.ready && dcache_c_q.io.count === 0.U
|
||||
dcache_tl.c <> dcache_c_q.io.deq
|
||||
dcache_c_q.io.enq.valid := spike.io.dcache.c.valid
|
||||
dcache_c_q.io.enq.bits := Mux(spike.io.dcache.c.voluntary,
|
||||
dcacheEdge.Release(
|
||||
fromSource = spike.io.dcache.c.sourceid,
|
||||
toAddress = spike.io.dcache.c.address,
|
||||
lgSize = blockBits.U,
|
||||
shrinkPermissions = spike.io.dcache.c.param,
|
||||
data = spike.io.dcache.c.data.asUInt)._2,
|
||||
Mux(spike.io.dcache.c.has_data,
|
||||
dcacheEdge.ProbeAck(
|
||||
spike.io.dcache.c.ready := dcache_tl.c.ready
|
||||
dcache_tl.c.valid := spike.io.dcache.c.valid
|
||||
if (dcacheEdge.manager.anySupportAcquireB) {
|
||||
dcache_tl.c.bits := Mux(spike.io.dcache.c.voluntary,
|
||||
dcacheEdge.Release(
|
||||
fromSource = spike.io.dcache.c.sourceid,
|
||||
toAddress = spike.io.dcache.c.address,
|
||||
lgSize = blockBits.U,
|
||||
reportPermissions = spike.io.dcache.c.param,
|
||||
data = spike.io.dcache.c.data.asUInt),
|
||||
dcacheEdge.ProbeAck(
|
||||
fromSource = spike.io.dcache.c.sourceid,
|
||||
toAddress = spike.io.dcache.c.address,
|
||||
lgSize = blockBits.U,
|
||||
reportPermissions = spike.io.dcache.c.param)
|
||||
))
|
||||
shrinkPermissions = spike.io.dcache.c.param,
|
||||
data = spike.io.dcache.c.data.asUInt)._2,
|
||||
Mux(spike.io.dcache.c.has_data,
|
||||
dcacheEdge.ProbeAck(
|
||||
fromSource = spike.io.dcache.c.sourceid,
|
||||
toAddress = spike.io.dcache.c.address,
|
||||
lgSize = blockBits.U,
|
||||
reportPermissions = spike.io.dcache.c.param,
|
||||
data = spike.io.dcache.c.data.asUInt),
|
||||
dcacheEdge.ProbeAck(
|
||||
fromSource = spike.io.dcache.c.sourceid,
|
||||
toAddress = spike.io.dcache.c.address,
|
||||
lgSize = blockBits.U,
|
||||
reportPermissions = spike.io.dcache.c.param)
|
||||
))
|
||||
} else {
|
||||
dcache_tl.c.bits := DontCare
|
||||
}
|
||||
|
||||
val has_data = dcacheEdge.hasData(dcache_tl.d.bits)
|
||||
val should_finish = dcacheEdge.isRequest(dcache_tl.d.bits)
|
||||
@@ -376,12 +419,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
|
||||
dcache_tl.e.valid := dcache_tl.d.valid && should_finish
|
||||
dcache_tl.e.bits := dcacheEdge.GrantAck(dcache_tl.d.bits)
|
||||
|
||||
val mmio_a_q = Module(new Queue(new TLBundleA(mmioEdge.bundle), 1, flow=true, pipe=true))
|
||||
spike.io.mmio.a.ready := mmio_a_q.io.enq.ready && mmio_a_q.io.count === 0.U
|
||||
mmio_tl.a <> mmio_a_q.io.deq
|
||||
mmio_a_q.io.enq.valid := spike.io.mmio.a.valid
|
||||
spike.io.mmio.a.ready := mmio_tl.a.ready
|
||||
mmio_tl.a.valid := spike.io.mmio.a.valid
|
||||
val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U })
|
||||
mmio_a_q.io.enq.bits := Mux(spike.io.mmio.a.store,
|
||||
mmio_tl.a.bits := Mux(spike.io.mmio.a.store,
|
||||
mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2,
|
||||
mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2)
|
||||
|
||||
@@ -389,9 +430,33 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
|
||||
spike.io.mmio.d.valid := mmio_tl.d.valid
|
||||
spike.io.mmio.d.data := mmio_tl.d.bits.data
|
||||
|
||||
spike.io.tcm := DontCare
|
||||
spike.io.tcm.a.valid := false.B
|
||||
spike.io.tcm.d.ready := true.B
|
||||
outer.tcmNode.map { tcmNode =>
|
||||
val (tcm_tl, tcmEdge) = tcmNode.in(0)
|
||||
val debug_tcm_tl = WireInit(tcm_tl)
|
||||
dontTouch(debug_tcm_tl)
|
||||
tcm_tl.a.ready := true.B
|
||||
spike.io.tcm.a.valid := tcm_tl.a.valid
|
||||
spike.io.tcm.a.address := tcm_tl.a.bits.address
|
||||
spike.io.tcm.a.data := tcm_tl.a.bits.data
|
||||
spike.io.tcm.a.mask := tcm_tl.a.bits.mask
|
||||
spike.io.tcm.a.opcode := tcm_tl.a.bits.opcode
|
||||
spike.io.tcm.a.size := tcm_tl.a.bits.size
|
||||
|
||||
spike.io.tcm.d.ready := tcm_tl.d.ready
|
||||
tcm_tl.d.bits := tcmEdge.AccessAck(RegNext(tcm_tl.a.bits))
|
||||
when (RegNext(tcm_tl.a.bits.opcode === TLMessages.Get)) {
|
||||
tcm_tl.d.bits.opcode := TLMessages.AccessAckData
|
||||
}
|
||||
tcm_tl.d.valid := spike.io.tcm.d.valid
|
||||
tcm_tl.d.bits.data := spike.io.tcm.d.data
|
||||
}
|
||||
}
|
||||
|
||||
class WithNSpikeCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
|
||||
class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(),
|
||||
overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
|
||||
case TilesLocated(InSubsystem) => {
|
||||
// Calculate the next available hart ID (since hart ID cannot be duplicated)
|
||||
val prev = up(TilesLocated(InSubsystem), site)
|
||||
@@ -399,8 +464,21 @@ class WithNSpikeCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
|
||||
// Create TileAttachParams for every core to be instantiated
|
||||
(0 until n).map { i =>
|
||||
SpikeTileAttachParams(
|
||||
tileParams = SpikeTileParams(hartId = i + idOffset)
|
||||
tileParams = tileParams.copy(hartId = i + idOffset)
|
||||
)
|
||||
} ++ prev
|
||||
}
|
||||
})
|
||||
|
||||
class WithSpikeTCM extends Config((site, here, up) => {
|
||||
case TilesLocated(InSubsystem) => {
|
||||
val prev = up(TilesLocated(InSubsystem))
|
||||
require(prev.size == 1)
|
||||
val spike = prev(0).asInstanceOf[SpikeTileAttachParams]
|
||||
Seq(spike.copy(tileParams = spike.tileParams.copy(
|
||||
tcmParams = Some(up(ExtMem).get.master)
|
||||
)))
|
||||
}
|
||||
case ExtMem => None
|
||||
case BankedL2Key => up(BankedL2Key).copy(nBanks = 0)
|
||||
})
|
||||
|
||||
@@ -12,6 +12,7 @@ import freechips.rocketchip.prci._
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
|
||||
import sifive.blocks.devices.uart.{HasPeripheryUART, PeripheryUARTKey}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.tile._
|
||||
import freechips.rocketchip.tilelink._
|
||||
@@ -45,9 +46,33 @@ trait CanHaveHTIF { this: BaseSubsystem =>
|
||||
}
|
||||
}
|
||||
|
||||
// This trait adds the "chosen" node to DTS, which
|
||||
// can be used to pass information to OS about the earlycon
|
||||
case object ChosenInDTS extends Field[Boolean](true)
|
||||
trait CanHaveChosenInDTS { this: BaseSubsystem =>
|
||||
if (p(ChosenInDTS)) {
|
||||
this match {
|
||||
case t: HasPeripheryUART if (!p(PeripheryUARTKey).isEmpty) => {
|
||||
val chosen = new Device {
|
||||
def describe(resources: ResourceBindings): Description = {
|
||||
val stdout = resources("stdout").map(_.value)
|
||||
Description("chosen", resources("uart").headOption.map { case Binding(_, value) =>
|
||||
"stdout-path" -> Seq(value)
|
||||
}.toMap)
|
||||
}
|
||||
}
|
||||
ResourceBinding {
|
||||
t.uarts.foreach(u => Resource(chosen, "uart").bind(ResourceAlias(u.device.label)))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
|
||||
with HasTiles
|
||||
with CanHaveHTIF
|
||||
with CanHaveChosenInDTS
|
||||
{
|
||||
def coreMonitorBundles = tiles.map {
|
||||
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
|
||||
|
||||
@@ -60,4 +60,5 @@ class AbstractConfig extends Config(
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
|
||||
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
|
||||
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
|
||||
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
|
||||
|
||||
@@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
|
||||
|
||||
// DOC include start: FFTRocketConfig
|
||||
class FFTRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC
|
||||
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
@@ -58,6 +59,7 @@ class LargeNVDLARocketConfig extends Config(
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class ManyMMIOAcceleratorRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC
|
||||
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
|
||||
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
|
||||
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
|
||||
|
||||
@@ -21,6 +21,18 @@ class FPGemminiRocketConfig extends Config(
|
||||
new chipyard.config.WithSystemBusWidth(128) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class LeanGemminiRocketConfig extends Config(
|
||||
new gemmini.LeanGemminiConfig ++ // use Lean Gemmini systolic array GEMM accelerator
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new chipyard.config.WithSystemBusWidth(128) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class LeanGemminiPrintfRocketConfig extends Config(
|
||||
new gemmini.LeanGemminiPrintfConfig ++ // use Lean Gemmini systolic array GEMM accelerator
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new chipyard.config.WithSystemBusWidth(128) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class HwachaRocketConfig extends Config(
|
||||
new chipyard.config.WithHwachaTest ++
|
||||
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
|
||||
|
||||
@@ -15,6 +15,7 @@ class RocketConfig extends Config(
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
class TinyRocketConfig extends Config(
|
||||
new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports
|
||||
new chipyard.config.WithTLSerialLocation(
|
||||
freechips.rocketchip.subsystem.FBUS,
|
||||
freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses
|
||||
@@ -133,3 +134,9 @@ class MulticlockAXIOverSerialConfig extends Config(
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
// DOC include end: MulticlockAXIOverSerialConfig
|
||||
|
||||
class CustomIOChipTopRocketConfig extends Config(
|
||||
new chipyard.example.WithCustomChipTop ++
|
||||
new chipyard.example.WithCustomIOCells ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
package chipyard
|
||||
|
||||
import freechips.rocketchip.config.{Config}
|
||||
import freechips.rocketchip.rocket.{DCacheParams}
|
||||
|
||||
// Configs which instantiate a Spike-simulated
|
||||
// tile that interacts with the Chipyard SoC
|
||||
@@ -14,6 +15,33 @@ class SpikeConfig extends Config(
|
||||
class SpikeFastUARTConfig extends Config(
|
||||
new chipyard.WithNSpikeCores(1) ++
|
||||
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
|
||||
new chipyard.config.WithMemoryBusFrequency(1) ++
|
||||
new chipyard.config.WithPeripheryBusFrequency(1) ++
|
||||
new chipyard.config.WithMemoryBusFrequency(2) ++
|
||||
new chipyard.config.WithPeripheryBusFrequency(2) ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// Makes the UART fast, also builds no L2 and a ludicrous L1D
|
||||
class SpikeUltraFastConfig extends Config(
|
||||
new chipyard.WithSpikeTCM ++
|
||||
new chipyard.WithNSpikeCores(1) ++
|
||||
new testchipip.WithSerialPBusMem ++
|
||||
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
|
||||
new chipyard.config.WithMemoryBusFrequency(2) ++
|
||||
new chipyard.config.WithPeripheryBusFrequency(2) ++
|
||||
new chipyard.config.WithBroadcastManager ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
// Add the default firechip devices
|
||||
class SpikeUltraFastDevicesConfig extends Config(
|
||||
new chipyard.harness.WithSimBlockDevice ++
|
||||
new chipyard.harness.WithLoopbackNIC ++
|
||||
new icenet.WithIceNIC ++
|
||||
new testchipip.WithBlockDevice ++
|
||||
|
||||
new chipyard.WithSpikeTCM ++
|
||||
new chipyard.WithNSpikeCores(1) ++
|
||||
new testchipip.WithSerialPBusMem ++
|
||||
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
|
||||
new chipyard.config.WithMemoryBusFrequency(2) ++
|
||||
new chipyard.config.WithPeripheryBusFrequency(2) ++
|
||||
new chipyard.config.WithBroadcastManager ++
|
||||
new chipyard.config.AbstractConfig)
|
||||
|
||||
@@ -77,6 +77,7 @@ class TutorialSha3BlackBoxConfig extends Config(
|
||||
|
||||
// Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
|
||||
class TutorialNoCConfig extends Config(
|
||||
new chipyard.iobinders.WithDontTouchIOBinders(false) ++
|
||||
// Try changing the dimensions of the Mesh topology
|
||||
new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams(
|
||||
NoCParams(
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
package chipyard.example
|
||||
|
||||
import chisel3._
|
||||
import chipyard.iobinders._
|
||||
|
||||
import freechips.rocketchip.config._
|
||||
import freechips.rocketchip.diplomacy.{InModuleBody}
|
||||
import barstools.iocell.chisel._
|
||||
import chipyard._
|
||||
|
||||
// A "custom" IOCell with additional I/O
|
||||
// The IO don't do anything here in this example
|
||||
class CustomDigitalInIOCellBundle extends DigitalInIOCellBundle {
|
||||
val custom_out = Output(Bool())
|
||||
val custom_in = Input(Bool())
|
||||
}
|
||||
|
||||
// Using a custom digital in iocell instead of the default one
|
||||
class CustomDigitalInIOCell extends RawModule with DigitalInIOCell {
|
||||
val io = IO(new CustomDigitalInIOCellBundle)
|
||||
io.i := io.pad
|
||||
io.custom_out := io.pad
|
||||
}
|
||||
|
||||
case class CustomIOCellParams() extends IOCellTypeParams {
|
||||
def analog() = Module(new GenericAnalogIOCell)
|
||||
def gpio() = Module(new GenericDigitalGPIOCell)
|
||||
def input() = Module(new CustomDigitalInIOCell)
|
||||
def output() = Module(new GenericDigitalOutIOCell)
|
||||
}
|
||||
|
||||
class CustomChipTop(implicit p: Parameters) extends ChipTop {
|
||||
// making the module name ChipTop instead of CustomChipTop means
|
||||
// we don't have to set the TOP make variable to CustomChipTop
|
||||
override lazy val desiredName = "ChipTop"
|
||||
|
||||
// InModuleBody blocks are executed within the LazyModuleImp of this block
|
||||
InModuleBody {
|
||||
iocellMap.foreach { case (interface, cells) => {
|
||||
cells.foreach { _ match {
|
||||
case c: CustomDigitalInIOCell => {
|
||||
c.io.custom_in := false.B
|
||||
}
|
||||
case c: GenericDigitalOutIOCell => {
|
||||
// do nothing
|
||||
}
|
||||
case c => {
|
||||
require(false, "Unsupported iocell type ${c.getClass}")
|
||||
}
|
||||
}}
|
||||
}}
|
||||
|
||||
// demonstrate accessing the iocellMap directly
|
||||
val serialTLIOCells = iocellMap("interface testchipip.CanHavePeripheryTLSerial")
|
||||
}
|
||||
}
|
||||
|
||||
class WithCustomIOCells extends Config((site, here, up) => {
|
||||
case IOCellKey => CustomIOCellParams()
|
||||
})
|
||||
|
||||
class WithCustomChipTop extends Config((site, here, up) => {
|
||||
case BuildTop => (p: Parameters) => new CustomChipTop()(p)
|
||||
})
|
||||
@@ -235,6 +235,18 @@ class FireSimGemminiRocketConfig extends Config(
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.GemminiRocketConfig)
|
||||
|
||||
class FireSimLeanGemminiRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.LeanGemminiRocketConfig)
|
||||
|
||||
class FireSimLeanGemminiPrintfRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.LeanGemminiPrintfRocketConfig)
|
||||
|
||||
//**********************************************************************************
|
||||
// Supernode Configurations, base off chipyard's RocketConfig
|
||||
//**********************************************************************************
|
||||
@@ -288,3 +300,9 @@ class FireSimRocketMMIOOnlyConfig extends Config(
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.RocketConfig)
|
||||
|
||||
class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config(
|
||||
new WithDefaultMMIOOnlyFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.LeanGemminiRocketConfig)
|
||||
|
||||
Submodule generators/gemmini updated: 9e478ecce9...4dd19f3e93
Submodule generators/ibex updated: 5a512227d8...626127f229
Submodule generators/sha3 updated: 98089ba372...8c5d244303
Submodule generators/sifive-blocks updated: 4273925fdd...3938f301ce
Submodule generators/testchipip updated: 802d2b4a4d...dead693f8f
@@ -111,4 +111,11 @@ if [ $TOOLCHAIN == "riscv-tools" ]; then
|
||||
make -C $RDIR/generators/gemmini/software/libgemmini install
|
||||
fi
|
||||
|
||||
echo '==> Installing DRAMSim2 Shared Library'
|
||||
cd $RDIR
|
||||
git submodule update --init tools/DRAMSim2
|
||||
cd tools/DRAMSim2
|
||||
make libdramsim.so
|
||||
cp libdramsim.so $RISCV/lib/
|
||||
|
||||
echo "Extra Toolchain Utilities/Tests Build Complete!"
|
||||
|
||||
@@ -106,8 +106,6 @@ cd "$RDIR"
|
||||
software/coremark \
|
||||
software/firemarshal \
|
||||
software/spec2017 \
|
||||
vlsi/hammer-cadence-plugins \
|
||||
vlsi/hammer-synopsys-plugins \
|
||||
vlsi/hammer-mentor-plugins \
|
||||
fpga/fpga-shells
|
||||
do
|
||||
|
||||
@@ -12,10 +12,6 @@ fi
|
||||
|
||||
# Initialize HAMMER CAD-plugins
|
||||
if [[ $1 != *openroad* ]] && [[ $2 != *openroad* ]]; then
|
||||
git submodule update --init --recursive vlsi/hammer-cadence-plugins
|
||||
pip install -e vlsi/hammer-cadence-plugins
|
||||
git submodule update --init --recursive vlsi/hammer-synopsys-plugins
|
||||
pip install -e vlsi/hammer-synopsys-plugins
|
||||
git submodule update --init --recursive vlsi/hammer-mentor-plugins
|
||||
pip install -e vlsi/hammer-mentor-plugins
|
||||
fi
|
||||
|
||||
Submodule sims/firesim updated: 69e428f010...68e5113887
3
sims/xcelium/.gitignore
vendored
Normal file
3
sims/xcelium/.gitignore
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
*
|
||||
!.gitignore
|
||||
*Makefile
|
||||
140
sims/xcelium/Makefile
Normal file
140
sims/xcelium/Makefile
Normal file
@@ -0,0 +1,140 @@
|
||||
#########################################################################################
|
||||
# xcelium makefile
|
||||
#########################################################################################
|
||||
|
||||
define CAD_INFO_HEADER
|
||||
# --------------------------------------------------------------------------------
|
||||
# This script was written and developed by Chipyard at UC Berkeley; however, the
|
||||
# underlying commands and reports are copyrighted by Cadence. We thank Cadence for
|
||||
# granting permission to share our research to help promote and foster the next
|
||||
# generation of innovators.
|
||||
# --------------------------------------------------------------------------------
|
||||
endef
|
||||
|
||||
export CAD_INFO_HEADER
|
||||
|
||||
#########################################################################################
|
||||
# general path variables
|
||||
#########################################################################################
|
||||
base_dir=$(abspath ../..)
|
||||
sim_dir=$(abspath .)
|
||||
|
||||
#########################################################################################
|
||||
# include shared variables
|
||||
#########################################################################################
|
||||
include $(base_dir)/variables.mk
|
||||
|
||||
#########################################################################################
|
||||
# name of simulator (used to generate *.f arguments file)
|
||||
#########################################################################################
|
||||
sim_name = xrun
|
||||
|
||||
#########################################################################################
|
||||
# xcelium simulator types and rules
|
||||
#########################################################################################
|
||||
sim_prefix = simx
|
||||
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
|
||||
sim_debug = $(sim)-debug
|
||||
sim_workdir = $(build_dir)/xcelium.d
|
||||
sim_run_tcl = $(build_dir)/xcelium_run.tcl
|
||||
sim_debug_run_tcl = $(build_dir)/xcelium_debug_run.tcl
|
||||
|
||||
include $(base_dir)/xcelium.mk
|
||||
|
||||
.PHONY: default debug
|
||||
default: $(sim)
|
||||
debug: $(sim_debug)
|
||||
|
||||
#########################################################################################
|
||||
# simulation requirements
|
||||
#########################################################################################
|
||||
SIM_FILE_REQS += \
|
||||
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
|
||||
|
||||
# copy files but ignore *.h files in *.f since xcelium has -Wcxx include
|
||||
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
|
||||
cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
|
||||
$(foreach file,\
|
||||
$(SIM_FILE_REQS),\
|
||||
$(if $(filter %.h,$(file)),\
|
||||
,\
|
||||
echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
|
||||
|
||||
#########################################################################################
|
||||
# import other necessary rules and variables
|
||||
#########################################################################################
|
||||
include $(base_dir)/common.mk
|
||||
|
||||
#########################################################################################
|
||||
# xcelium binary and arguments
|
||||
#########################################################################################
|
||||
XCELIUM = xrun
|
||||
XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
|
||||
|
||||
#########################################################################################
|
||||
# xcelium build paths
|
||||
#########################################################################################
|
||||
model_dir = $(build_dir)/$(long_name)
|
||||
model_dir_debug = $(build_dir)/$(long_name).debug
|
||||
|
||||
|
||||
#########################################################################################
|
||||
# xcelium simulator rules
|
||||
#########################################################################################
|
||||
|
||||
$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
|
||||
rm -rf $(model_dir)
|
||||
$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
|
||||
|
||||
$(sim_run_tcl): $(sim_workdir)
|
||||
echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
|
||||
echo "run" >> $(sim_run_tcl)
|
||||
echo "exit" >> $(sim_run_tcl)
|
||||
|
||||
# The system libstdc++ may not link correctly with some of our dynamic libs, so
|
||||
# force loading the conda one (if present) with LD_PRELOAD
|
||||
$(sim): $(sim_workdir) $(sim_run_tcl)
|
||||
echo "#!/usr/bin/env bash" > $(sim)
|
||||
echo "$$CAD_INFO_HEADER" >> $(sim)
|
||||
cat arg-reshuffle >> $(sim)
|
||||
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
|
||||
chmod +x $(sim)
|
||||
|
||||
$(sim_debug_run_tcl): $(sim_workdir)
|
||||
echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
|
||||
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
|
||||
echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
|
||||
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
|
||||
echo "run" >> $(sim_debug_run_tcl)
|
||||
echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
|
||||
echo "exit" >> $(sim_debug_run_tcl)
|
||||
|
||||
|
||||
$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
|
||||
echo "#!/usr/bin/env bash" > $(sim_debug)
|
||||
echo "$$CAD_INFO_HEADER" >> $(sim_debug)
|
||||
cat arg-reshuffle >> $(sim_debug)
|
||||
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
|
||||
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
|
||||
chmod +x $(sim_debug)
|
||||
|
||||
|
||||
#########################################################################################
|
||||
# create vcd rules
|
||||
#########################################################################################
|
||||
.PRECIOUS: $(output_dir)/%.vcd %.vcd
|
||||
$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
|
||||
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
|
||||
|
||||
#########################################################################################
|
||||
# general cleanup rules
|
||||
#########################################################################################
|
||||
.PHONY: clean clean-sim clean-sim-debug
|
||||
clean:
|
||||
rm -rf $(gen_dir) $(sim_prefix)-*
|
||||
|
||||
clean-sim:
|
||||
rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
|
||||
|
||||
clean-sim-debug:
|
||||
rm -rf $(model_dir_debug) $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
|
||||
30
sims/xcelium/arg-reshuffle
Executable file
30
sims/xcelium/arg-reshuffle
Executable file
@@ -0,0 +1,30 @@
|
||||
|
||||
# this is a wrapper that is copied into xcelium sim run scripts that
|
||||
# re-maps arguments from the argument pattern used by other
|
||||
# simulators (vcs, verilator) to the pattern required by xcelium.
|
||||
#
|
||||
# mainly:
|
||||
# * +vcdfile=VAL -> XCELIUM_WAVEFORM_FLAG=VAL, to be passed in as env var
|
||||
# * arguments not prefixed with a + or - are treated as the arguments to
|
||||
# the target and are passed in instead with the +target-argument plusarg
|
||||
|
||||
regular_args=""
|
||||
target_args="+permissive"
|
||||
for var in "$@"
|
||||
do
|
||||
if [[ $var = -* ]] || [[ $var = +* ]]
|
||||
then
|
||||
if [[ $var = +vcdfile=* ]]
|
||||
then
|
||||
XCELIUM_WAVEFORM_FLAG=${var/+vcdfile=/""}
|
||||
else
|
||||
regular_args="$regular_args $var"
|
||||
fi
|
||||
else
|
||||
target_args="$target_args +target-argument=$var"
|
||||
fi
|
||||
done
|
||||
target_args="$target_args +permissive-off"
|
||||
|
||||
INPUT_ARGS="$regular_args $target_args"
|
||||
|
||||
Submodule software/firemarshal updated: 8e02b02d14...fb93e3116f
@@ -6,7 +6,8 @@ LDFLAGS= -static
|
||||
include libgloss.mk
|
||||
|
||||
PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
|
||||
streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd
|
||||
streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \
|
||||
hello
|
||||
|
||||
spiflash.img: spiflash.py
|
||||
python3 $<
|
||||
|
||||
6
tests/hello.c
Normal file
6
tests/hello.c
Normal file
@@ -0,0 +1,6 @@
|
||||
#include <stdio.h>
|
||||
|
||||
int main(void) {
|
||||
printf("Hello world\n");
|
||||
return 0;
|
||||
}
|
||||
Submodule toolchains/riscv-tools/riscv-isa-sim updated: e7d6aff19a...d70ea67df7
@@ -159,6 +159,7 @@ endif
|
||||
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
|
||||
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
|
||||
EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extra.anno.json
|
||||
CHISEL_LOG_FILE ?= $(build_dir)/$(long_name).chisel.log
|
||||
|
||||
# chisel anno modification output
|
||||
MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json
|
||||
@@ -234,7 +235,7 @@ SBT_CLIENT_FLAG = --client
|
||||
endif
|
||||
|
||||
# passes $(JAVA_TOOL_OPTIONS) from env to java
|
||||
export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/
|
||||
export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always
|
||||
SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
|
||||
SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG)
|
||||
SBT_NON_THIN = $(subst $(SBT_CLIENT_FLAG),,$(SBT))
|
||||
|
||||
@@ -46,9 +46,9 @@ VLSI_MODEL_DUT_NAME ?= chiptop
|
||||
# If overriding, this should be relative to $(vlsi_dir)
|
||||
VLSI_OBJ_DIR ?= build
|
||||
ifneq ($(CUSTOM_VLOG),)
|
||||
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
|
||||
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
|
||||
else
|
||||
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
|
||||
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP)
|
||||
endif
|
||||
|
||||
#########################################################################################
|
||||
@@ -118,6 +118,12 @@ endif
|
||||
|
||||
$(SYN_CONF): $(VLSI_RTL)
|
||||
mkdir -p $(dir $@)
|
||||
echo "sim.inputs:" > $@
|
||||
echo " input_files:" >> $@
|
||||
for x in $$(cat $(VLSI_RTL)); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " input_files_meta: 'append'" >> $@
|
||||
echo "synthesis.inputs:" >> $@
|
||||
echo " top_module: $(VLSI_TOP)" >> $@
|
||||
echo " input_files:" >> $@
|
||||
|
||||
@@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints:
|
||||
right: 0
|
||||
top: 0
|
||||
bottom: 0
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 550
|
||||
y: 25
|
||||
orientation: "r0"
|
||||
top_layer: "M4"
|
||||
master: "SRAM1RW4096x8"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
|
||||
type: hardmacro
|
||||
x: 550
|
||||
y: 270
|
||||
orientation: "r0"
|
||||
top_layer: "M4"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
|
||||
type: hardmacro
|
||||
x: 675
|
||||
y: 25
|
||||
orientation: "r0"
|
||||
top_layer: "M4"
|
||||
master: "SRAM1RW4096x8"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
|
||||
type: hardmacro
|
||||
x: 675
|
||||
y: 270
|
||||
orientation: "r0"
|
||||
top_layer: "M4"
|
||||
master: "SRAM1RW4096x8"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 125
|
||||
y: 150
|
||||
orientation: "my"
|
||||
top_layer: "M4"
|
||||
master: "SRAM1RW64x21"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 0
|
||||
y: 25
|
||||
orientation: "my"
|
||||
top_layer: "M4"
|
||||
master: "SRAM1RW1024x32"
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 0
|
||||
y: 260
|
||||
orientation: "my"
|
||||
top_layer: "M4"
|
||||
master: "SRAM1RW1024x37"
|
||||
|
||||
# Pin placement constraints
|
||||
vlsi.inputs.pin_mode: generated
|
||||
|
||||
@@ -2,149 +2,18 @@
|
||||
|
||||
# Specify clock signals
|
||||
vlsi.inputs.clocks: [
|
||||
{name: "clock_clock", period: "5ns", uncertainty: "1ns"}
|
||||
{name: "clock_clock", period: "30ns", uncertainty: "2ns"}
|
||||
]
|
||||
|
||||
# Power Straps
|
||||
par.power_straps_mode: generate
|
||||
par.generate_power_straps_method: by_tracks
|
||||
par.blockage_spacing: 40.0
|
||||
par.blockage_spacing_top_layer: met4
|
||||
par.generate_power_straps_options:
|
||||
by_tracks:
|
||||
strap_layers:
|
||||
- met4
|
||||
- met5
|
||||
pin_layers:
|
||||
- met5
|
||||
blockage_spacing_met2: 4.0
|
||||
blockage_spacing_met4: 2.0
|
||||
track_width: 3
|
||||
track_width_met5: 1
|
||||
track_spacing: 5
|
||||
track_start: 10
|
||||
track_start_met5: 1
|
||||
power_utilization: 0.1
|
||||
power_utilization_met4: 0.1
|
||||
power_utilization_met5: 0.1
|
||||
|
||||
# Placement Constraints
|
||||
vlsi.inputs.placement_constraints:
|
||||
- path: "ChipTop"
|
||||
type: toplevel
|
||||
x: 0
|
||||
y: 0
|
||||
width: 4000
|
||||
height: 2500
|
||||
margins:
|
||||
left: 0
|
||||
right: 0
|
||||
top: 0
|
||||
bottom: 0
|
||||
|
||||
# Place data cache SRAM instances
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 100
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 700
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1300
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1900
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 1900
|
||||
orientation: r0
|
||||
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 1300
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 700
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 100
|
||||
orientation: r0
|
||||
|
||||
# Place instruction cache SRAM instances
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 3250
|
||||
y: 100
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
|
||||
type: hardmacro
|
||||
x: 3250
|
||||
y: 700
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 3450
|
||||
y: 1300
|
||||
orientation: r0
|
||||
|
||||
# Place L2 TLB SRAM instances
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 2000
|
||||
y: 1300
|
||||
orientation: "r0"
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
|
||||
type: hardmacro
|
||||
x: 2000
|
||||
y: 1900
|
||||
orientation: "r0"
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
|
||||
type: hardmacro
|
||||
x: 2750
|
||||
y: 1300
|
||||
orientation: "r0"
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
|
||||
type: hardmacro
|
||||
x: 2750
|
||||
y: 1900
|
||||
orientation: "r0"
|
||||
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
|
||||
type: hardmacro
|
||||
x: 3460
|
||||
y: 1900
|
||||
orientation: "r0"
|
||||
|
||||
# Pin placement constraints
|
||||
vlsi.inputs.pin_mode: generated
|
||||
vlsi.inputs.pin.generate_mode: semi_auto
|
||||
vlsi.inputs.pin.assignments: [
|
||||
{pins: "*", layers: ["met2", "met4"], side: "bottom"}
|
||||
]
|
||||
# If overriding the placement constraints in example-sky130.yml,
|
||||
# ensure one of the toplevel margin sides corresponding with the power pin metal layers
|
||||
# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
|
||||
# For example, in example-sky130.yml we set
|
||||
# par.generate_power_straps_options.by_tracks.pin_layers: 'met5' # horizontal layer
|
||||
# therefore we must also set:
|
||||
# vlsi.inputs.placement_constraints:
|
||||
# - path: "ChipTop"
|
||||
# ...
|
||||
# margins:
|
||||
# right: 0 # or left: 0
|
||||
60
vlsi/example-designs/sky130-openroad-rockettile.yml
Normal file
60
vlsi/example-designs/sky130-openroad-rockettile.yml
Normal file
@@ -0,0 +1,60 @@
|
||||
# Override configurations in ../example-sky130.yml and example-designs
|
||||
|
||||
# Specify clock signals
|
||||
# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
|
||||
vlsi.inputs.clocks: [
|
||||
{name: "clock", period: "30ns", uncertainty: "3ns"}
|
||||
]
|
||||
|
||||
# Placement Constraints
|
||||
# Placement Constraints
|
||||
vlsi.inputs.placement_constraints:
|
||||
- path: "RocketTile"
|
||||
type: toplevel
|
||||
x: 0
|
||||
y: 0
|
||||
width: 4000
|
||||
height: 3000
|
||||
margins:
|
||||
left: 10
|
||||
right: 0
|
||||
top: 10
|
||||
bottom: 10
|
||||
|
||||
# Place SRAM memory instances
|
||||
# SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
|
||||
# data cache
|
||||
- path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 50
|
||||
orientation: r90
|
||||
- path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 450
|
||||
orientation: r90
|
||||
- path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 850
|
||||
orientation: r90
|
||||
- path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1250
|
||||
orientation: r90
|
||||
|
||||
# tag array
|
||||
- path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1600
|
||||
orientation: r90
|
||||
|
||||
# instruction cache
|
||||
- path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 2100
|
||||
orientation: r90
|
||||
@@ -3,9 +3,42 @@
|
||||
# Specify clock signals
|
||||
# Relax the clock period for OpenROAD to meet timing
|
||||
vlsi.inputs.clocks: [
|
||||
{name: "clock_clock", period: "30ns", uncertainty: "1ns"}
|
||||
{name: "clock_clock", period: "50ns", uncertainty: "2ns"}
|
||||
]
|
||||
|
||||
# Flow parameters that yield a routable design with reasonable timing
|
||||
par.openroad:
|
||||
timing_driven: true # set to false to drastically speed up runs
|
||||
create_archive_mode: none
|
||||
|
||||
write_reports: true # set to false to slightly speed up runs
|
||||
|
||||
floorplan_mode: generate
|
||||
|
||||
macro_placement.halo: [50, 50]
|
||||
|
||||
global_placement.timing_driven: true
|
||||
global_placement.routability_driven: true
|
||||
|
||||
global_placement.placement_padding: 6
|
||||
detailed_placement.placement_padding: 4
|
||||
clock_tree.placement_padding: 2
|
||||
clock_tree_resize.placement_padding: 0
|
||||
|
||||
clock_tree_resize.setup_margin: 0.0
|
||||
clock_tree_resize.hold_margin: 0.20
|
||||
global_route_resize.hold_margin: 0.60
|
||||
clock_tree_resize.hold_max_buffer_percent: 80
|
||||
|
||||
global_placement.routing_adjustment: 0.5
|
||||
global_route.routing_adjustment: 0.3
|
||||
global_route_resize.routing_adjustment: 0.2
|
||||
|
||||
# DRC/LVS configuration
|
||||
drc.magic.generate_only: true
|
||||
lvs.netgen.generate_only: true
|
||||
|
||||
|
||||
# Placement Constraints
|
||||
vlsi.inputs.placement_constraints:
|
||||
- path: "ChipTop"
|
||||
@@ -13,78 +46,47 @@ vlsi.inputs.placement_constraints:
|
||||
x: 0
|
||||
y: 0
|
||||
width: 4000
|
||||
height: 2500
|
||||
height: 3000
|
||||
margins:
|
||||
left: 10
|
||||
right: 10
|
||||
right: 0
|
||||
top: 10
|
||||
bottom: 10
|
||||
|
||||
# Place data cache SRAM instances
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
|
||||
# Place SRAM memory instances
|
||||
# SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
|
||||
# data cache
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 100
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
|
||||
y: 50
|
||||
orientation: r90
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 700
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
|
||||
y: 450
|
||||
orientation: r90
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1300
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
|
||||
y: 850
|
||||
orientation: r90
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1900
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
|
||||
y: 1250
|
||||
orientation: r90
|
||||
|
||||
# tag array
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 1900
|
||||
orientation: r0
|
||||
x: 50
|
||||
y: 1600
|
||||
orientation: r90
|
||||
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
|
||||
# instruction cache
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 1300
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 700
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
|
||||
type: hardmacro
|
||||
x: 1000
|
||||
y: 100
|
||||
orientation: r0
|
||||
|
||||
# Place instruction cache SRAM instances
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
|
||||
type: hardmacro
|
||||
x: 3250
|
||||
y: 100
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
|
||||
type: hardmacro
|
||||
x: 3250
|
||||
y: 700
|
||||
orientation: r0
|
||||
|
||||
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
|
||||
type: hardmacro
|
||||
x: 3450
|
||||
y: 1300
|
||||
orientation: r0
|
||||
x: 50
|
||||
y: 2100
|
||||
orientation: r90
|
||||
|
||||
@@ -7,7 +7,7 @@ vlsi.core.max_threads: 12
|
||||
# Technology paths
|
||||
technology.sky130:
|
||||
sky130A: "/path/to/sky130A"
|
||||
openram_lib: "/path/to/sky130_sram_macros"
|
||||
sram22_sky130_macros: "/path/to/sram22_sky130_macros"
|
||||
|
||||
# this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
|
||||
sky130_nda: "/path/to/skywater-src-nda"
|
||||
@@ -20,31 +20,55 @@ vlsi.inputs.power_spec_type: "cpf"
|
||||
|
||||
# Specify clock signals
|
||||
vlsi.inputs.clocks: [
|
||||
{name: "clock_clock", period: "10ns", uncertainty: "1ns"}
|
||||
{name: "clock_clock", period: "20ns", uncertainty: "1ns"}
|
||||
]
|
||||
|
||||
# Generate Make include to aid in flow
|
||||
vlsi.core.build_system: make
|
||||
|
||||
|
||||
# Placement Constraints
|
||||
vlsi.inputs.placement_constraints:
|
||||
- path: "ChipTop"
|
||||
type: toplevel
|
||||
x: 0
|
||||
y: 0
|
||||
width: 3500
|
||||
height: 2500
|
||||
width: 4000
|
||||
height: 3000
|
||||
margins:
|
||||
left: 10
|
||||
right: 10
|
||||
right: 0
|
||||
top: 10
|
||||
bottom: 10
|
||||
|
||||
# Place SRAM memory instances
|
||||
# data cache
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 50
|
||||
orientation: r90
|
||||
|
||||
# tag array
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 1600
|
||||
orientation: r90
|
||||
|
||||
# instruction cache
|
||||
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
|
||||
type: hardmacro
|
||||
x: 50
|
||||
y: 2100
|
||||
orientation: r90
|
||||
|
||||
|
||||
# Power Straps
|
||||
par.power_straps_mode: generate
|
||||
par.generate_power_straps_method: by_tracks
|
||||
par.blockage_spacing: 40.0
|
||||
par.blockage_spacing_top_layer: met4
|
||||
par.blockage_spacing: 2.0
|
||||
par.blockage_spacing_top_layer: met3
|
||||
par.generate_power_straps_options:
|
||||
by_tracks:
|
||||
strap_layers:
|
||||
@@ -63,6 +87,7 @@ par.generate_power_straps_options:
|
||||
power_utilization_met4: 0.1
|
||||
power_utilization_met5: 0.1
|
||||
|
||||
|
||||
# Pin placement constraints
|
||||
vlsi.inputs.pin_mode: generated
|
||||
vlsi.inputs.pin.generate_mode: semi_auto
|
||||
@@ -70,5 +95,6 @@ vlsi.inputs.pin.assignments: [
|
||||
{pins: "*", layers: ["met2", "met4"], side: "bottom"}
|
||||
]
|
||||
|
||||
|
||||
# SRAM Compiler compiler options
|
||||
vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"
|
||||
|
||||
Submodule vlsi/hammer-cadence-plugins deleted from f9e323bd64
Submodule vlsi/hammer-synopsys-plugins deleted from e53fa5c51f
@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
|
||||
echo " top_module: $(VLSI_TOP)" >> $@
|
||||
echo " tb_name: ''" >> $@ # don't specify -top
|
||||
echo " input_files:" >> $@
|
||||
for x in $$(cat $(sim_common_files)); do \
|
||||
for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " input_files_meta: 'append'" >> $@
|
||||
|
||||
@@ -1,10 +1,8 @@
|
||||
#########################################################################################
|
||||
# makefile variables for Hammer tutorials
|
||||
#########################################################################################
|
||||
# tutorial ?= none
|
||||
tutorial ?= sky130-openroad
|
||||
|
||||
extra ?=
|
||||
tutorial ?= none
|
||||
EXTRA_CONFS ?=
|
||||
|
||||
# TODO: eventually have asap7 commercial/openroad tutorial flavors
|
||||
ifeq ($(tutorial),asap7)
|
||||
@@ -12,7 +10,7 @@ ifeq ($(tutorial),asap7)
|
||||
CONFIG ?= TinyRocketConfig
|
||||
TOOLS_CONF ?= example-tools.yml
|
||||
TECH_CONF ?= example-asap7.yml
|
||||
INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF)
|
||||
DESIGN_CONFS ?=
|
||||
VLSI_OBJ_DIR ?= build-asap7-commercial
|
||||
endif
|
||||
|
||||
@@ -21,9 +19,9 @@ ifeq ($(tutorial),sky130-commercial)
|
||||
CONFIG ?= TinyRocketConfig
|
||||
TOOLS_CONF ?= example-tools.yml
|
||||
TECH_CONF ?= example-sky130.yml
|
||||
DESIGN_CONF ?= example-designs/sky130-commercial.yml
|
||||
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
|
||||
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
|
||||
DESIGN_CONFS ?= example-designs/sky130-commercial.yml \
|
||||
$(if $(filter $(VLSI_TOP),Rocket), \
|
||||
example-designs/sky130-rocket.yml, )
|
||||
VLSI_OBJ_DIR ?= build-sky130-commercial
|
||||
endif
|
||||
|
||||
@@ -32,12 +30,14 @@ ifeq ($(tutorial),sky130-openroad)
|
||||
CONFIG ?= TinyRocketConfig
|
||||
TOOLS_CONF ?= example-openroad.yml
|
||||
TECH_CONF ?= example-sky130.yml
|
||||
DESIGN_CONF ?= example-designs/sky130-openroad.yml
|
||||
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
|
||||
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
|
||||
DESIGN_CONFS ?= example-designs/sky130-openroad.yml \
|
||||
$(if $(filter $(VLSI_TOP),Rocket), \
|
||||
example-designs/sky130-rocket.yml) \
|
||||
$(if $(filter $(VLSI_TOP),RocketTile), \
|
||||
example-designs/sky130-openroad-rockettile.yml, )
|
||||
VLSI_OBJ_DIR ?= build-sky130-openroad
|
||||
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
|
||||
ENABLE_YOSYS_FLOW = 1
|
||||
endif
|
||||
|
||||
HAMMER_EXTRA_ARGS ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)
|
||||
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
|
||||
|
||||
65
xcelium.mk
Normal file
65
xcelium.mk
Normal file
@@ -0,0 +1,65 @@
|
||||
|
||||
WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd
|
||||
|
||||
# If ntb_random_seed unspecified, xcelium uses 1 as constant seed.
|
||||
# Set ntb_random_seed_automatic to actually get a random seed
|
||||
ifdef RANDOM_SEED
|
||||
SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
|
||||
else
|
||||
SEED_FLAG=+ntb_random_seed_automatic
|
||||
endif
|
||||
|
||||
CLOCK_PERIOD ?= 1.0
|
||||
RESET_DELAY ?= 777.7
|
||||
|
||||
#----------------------------------------------------------------------------------------
|
||||
# gcc configuration/optimization
|
||||
#----------------------------------------------------------------------------------------
|
||||
include $(base_dir)/sims/common-sim-flags.mk
|
||||
|
||||
|
||||
XC_CXX_PREFIX=-Wcxx,
|
||||
XC_LD_PREFIX=-Wld,
|
||||
|
||||
REMOVE_RPATH=-Wl,-rpath%
|
||||
|
||||
XCELIUM_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS))
|
||||
XCELIUM_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS)))
|
||||
|
||||
XCELIUM_COMMON_ARGS = \
|
||||
-64bit \
|
||||
-xmlibdirname $(sim_workdir) \
|
||||
-l /dev/null \
|
||||
-log_xmsc_run /dev/null
|
||||
|
||||
XCELIUM_CC_OPTS = \
|
||||
$(XCELIUM_CXXFLAGS) \
|
||||
$(XCELIUM_LDFLAGS) \
|
||||
-enable_rpath
|
||||
|
||||
XCELIUM_NONCC_OPTS = \
|
||||
-fast_recompilation \
|
||||
-top $(TB) \
|
||||
-sv \
|
||||
-ALLOWREDEFINITION \
|
||||
-timescale 1ns/10ps \
|
||||
-define INTCNOPWR \
|
||||
-define INTC_NO_PWR_PINS \
|
||||
-define INTC_EMULATION \
|
||||
-f $(sim_common_files) \
|
||||
-glsperf \
|
||||
-notimingchecks \
|
||||
-delay_mode zero
|
||||
|
||||
PREPROC_DEFINES = \
|
||||
-define XCELIUM \
|
||||
-define CLOCK_PERIOD=$(CLOCK_PERIOD) \
|
||||
-define RESET_DELAY=$(RESET_DELAY) \
|
||||
-define PRINTF_COND=$(TB).printf_cond \
|
||||
-define STOP_COND=!$(TB).reset \
|
||||
-define MODEL=$(MODEL) \
|
||||
-define RANDOMIZE_MEM_INIT \
|
||||
-define RANDOMIZE_REG_INIT \
|
||||
-define RANDOMIZE_GARBAGE_ASSIGN \
|
||||
-define RANDOMIZE_INVALID_ASSIGN
|
||||
|
||||
Reference in New Issue
Block a user