Deprecate Dromajo in FireSim, use cospike
Move Cospike to testchipip
This commit is contained in:
abejgonzalez
@@ -1,508 +0,0 @@
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#include <cstdint>
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#include <vector>
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#include <string>
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#include <riscv/sim.h>
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#include <riscv/mmu.h>
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#include <riscv/encoding.h>
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#include <vpi_user.h>
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#include <svdpi.h>
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#include <sstream>
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#include <set>
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <sys/syscall.h>
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#include <fcntl.h>
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#if __has_include ("cospike_dtm.h")
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#define COSPIKE_DTM
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#include "testchip_dtm.h"
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extern testchip_dtm_t* dtm;
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bool spike_loadarch_done = false;
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#endif
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#if __has_include ("mm.h")
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#define COSPIKE_SIMDRAM
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#include "mm.h"
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extern std::map<long long int, backing_data_t> backing_mem_data;
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#endif
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#define CLINT_BASE (0x2000000)
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#define CLINT_SIZE (0x10000)
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#define UART_BASE (0x54000000)
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#define UART_SIZE (0x1000)
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#define PLIC_BASE (0xc000000)
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#define PLIC_SIZE (0x4000000)
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#define COSPIKE_PRINTF(...) { \
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printf(__VA_ARGS__); \
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fprintf(stderr, __VA_ARGS__); \
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}
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typedef struct system_info_t {
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std::string isa;
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int vlen;
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int pmpregions;
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uint64_t mem0_base;
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uint64_t mem0_size;
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int nharts;
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std::vector<char> bootrom;
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std::string priv;
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};
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class read_override_device_t : public abstract_device_t {
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public:
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read_override_device_t(std::string n, reg_t sz) : was_read_from(false), size(sz), name(n) { };
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virtual bool load(reg_t addr, size_t len, uint8_t* bytes) override {
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if (addr + len > size) return false;
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COSPIKE_PRINTF("Read from device %s at %lx\n", name.c_str(), addr);
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was_read_from = true;
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return true;
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}
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virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) override {
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COSPIKE_PRINTF("Store to device %s at %lx\n", name.c_str(), addr);
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return (addr + len <= size);
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}
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bool was_read_from;
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private:
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reg_t size;
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std::string name;
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};
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system_info_t* info = NULL;
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sim_t* sim = NULL;
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bool cospike_debug;
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reg_t tohost_addr = 0;
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reg_t fromhost_addr = 0;
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reg_t cospike_timeout = 0;
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std::set<reg_t> magic_addrs;
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cfg_t* cfg;
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std::vector<std::shared_ptr<read_override_device_t>> read_override_devices;
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static std::vector<std::pair<reg_t, abstract_mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
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{
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std::vector<std::pair<reg_t, abstract_mem_t*>> mems;
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mems.reserve(layout.size());
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for (const auto &cfg : layout) {
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mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size())));
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}
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return mems;
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}
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extern "C" void cospike_set_sysinfo(char* isa, int vlen, char* priv, int pmpregions,
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long long int mem0_base, long long int mem0_size,
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int nharts,
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char* bootrom
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) {
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if (!info) {
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info = new system_info_t;
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// technically the targets aren't zicntr compliant, but they implement the zicntr registers
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info->isa = std::string(isa) + "_zicntr";
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info->vlen = vlen;
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info->priv = std::string(priv);
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info->pmpregions = pmpregions;
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info->mem0_base = mem0_base;
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info->mem0_size = mem0_size;
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info->nharts = nharts;
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std::stringstream ss(bootrom);
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std::string s;
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while (ss >> s) {
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info->bootrom.push_back(std::stoi(s));
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}
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}
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}
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extern "C" void cospike_cosim(long long int cycle,
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long long int hartid,
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int has_wdata,
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int valid,
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long long int iaddr,
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unsigned long int insn,
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int raise_exception,
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int raise_interrupt,
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unsigned long long int cause,
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unsigned long long int wdata,
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int priv)
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{
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assert(info);
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if (unlikely(!sim)) {
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COSPIKE_PRINTF("Configuring spike cosim\n");
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std::vector<mem_cfg_t> mem_cfg;
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std::vector<size_t> hartids;
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mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size));
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for (int i = 0; i < info->nharts; i++)
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hartids.push_back(i);
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std::string visa = "vlen:" + std::to_string(info->vlen ? info->vlen : 128) + ",elen:64";
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cfg = new cfg_t(std::make_pair(0, 0),
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nullptr,
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info->isa.c_str(),
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info->priv.c_str(),
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visa.c_str(),
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false,
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endianness_little,
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info->pmpregions,
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mem_cfg,
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hartids,
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false,
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0
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);
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std::vector<std::pair<reg_t, abstract_mem_t*>> mems = make_mems(cfg->mem_layout());
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size_t default_boot_rom_size = 0x10000;
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size_t default_boot_rom_addr = 0x10000;
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assert(info->bootrom.size() < default_boot_rom_size);
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info->bootrom.resize(default_boot_rom_size);
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std::shared_ptr<rom_device_t> boot_rom = std::make_shared<rom_device_t>(info->bootrom);
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std::shared_ptr<mem_t> boot_addr_reg = std::make_shared<mem_t>(0x1000);
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uint64_t default_boot_addr = 0x80000000;
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boot_addr_reg.get()->store(0, 8, (const uint8_t*)(&default_boot_addr));
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std::shared_ptr<read_override_device_t> clint = std::make_shared<read_override_device_t>("clint", CLINT_SIZE);
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std::shared_ptr<read_override_device_t> uart = std::make_shared<read_override_device_t>("uart", UART_SIZE);
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std::shared_ptr<read_override_device_t> plic = std::make_shared<read_override_device_t>("plic", PLIC_SIZE);
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read_override_devices.push_back(clint);
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read_override_devices.push_back(uart);
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read_override_devices.push_back(plic);
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std::vector<std::pair<reg_t, std::shared_ptr<abstract_device_t>>> devices;
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// The device map is hardcoded here for now
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devices.push_back(std::pair(0x4000, boot_addr_reg));
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devices.push_back(std::pair(default_boot_rom_addr, boot_rom));
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devices.push_back(std::pair(CLINT_BASE, clint));
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devices.push_back(std::pair(UART_BASE, uart));
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devices.push_back(std::pair(PLIC_BASE, plic));
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s_vpi_vlog_info vinfo;
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if (!vpi_get_vlog_info(&vinfo))
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abort();
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std::vector<std::string> htif_args;
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bool in_permissive = false;
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cospike_debug = false;
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for (int i = 1; i < vinfo.argc; i++) {
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std::string arg(vinfo.argv[i]);
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if (arg == "+permissive") {
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in_permissive = true;
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} else if (arg == "+permissive-off") {
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in_permissive = false;
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} else if (arg == "+cospike_debug" || arg == "+cospike-debug") {
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cospike_debug = true;
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} else if (arg.find("+cospike-timeout=") == 0) {
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cospike_timeout = strtoull(arg.substr(17).c_str(), 0, 10);
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} else if (!in_permissive) {
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htif_args.push_back(arg);
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}
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}
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debug_module_config_t dm_config = {
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.progbufsize = 2,
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.max_sba_data_width = 0,
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.require_authentication = false,
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.abstract_rti = 0,
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.support_hasel = true,
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.support_abstract_csr_access = true,
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.support_abstract_fpr_access = true,
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.support_haltgroups = true,
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.support_impebreak = true
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};
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COSPIKE_PRINTF("isa string: %s\n", info->isa.c_str());
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COSPIKE_PRINTF("htif args: ");
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for (int i = 0; i < htif_args.size(); i++) {
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COSPIKE_PRINTF("%s", htif_args[i].c_str());
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}
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COSPIKE_PRINTF("\n");
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std::vector<const device_factory_t*> plugin_device_factories;
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sim = new sim_t(cfg, false,
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mems,
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plugin_device_factories,
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htif_args,
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dm_config,
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nullptr,
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false,
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nullptr,
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false,
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nullptr
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);
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for (auto &it : devices)
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sim->add_device(it.first, it.second);
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#ifdef COSPIKE_SIMDRAM
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// match sim_t's backing memory with the SimDRAM memory
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bus_t temp_mem_bus;
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for (auto& pair : mems) temp_mem_bus.add_device(pair.first, pair.second);
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for (auto& pair : backing_mem_data) {
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size_t base = pair.first;
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size_t size = pair.second.size;
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COSPIKE_PRINTF("Matching spike memory initial state for region %lx-%lx\n", base, base + size);
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if (!temp_mem_bus.store(base, size, pair.second.data)) {
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COSPIKE_PRINTF("Error, unable to match memory at address %lx\n", base);
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abort();
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}
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}
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#endif
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sim->configure_log(true, true);
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for (int i = 0; i < info->nharts; i++) {
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// Use our own reset vector
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sim->get_core(hartid)->get_state()->pc = 0x10040;
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// Set MMU to support up to sv39, as our normal hw configs do
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sim->get_core(hartid)->set_impl(IMPL_MMU_SV48, false);
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sim->get_core(hartid)->set_impl(IMPL_MMU_SV57, false);
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// HACKS: Our processor's don't implement zicntr fully, they don't provide time
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sim->get_core(hartid)->get_state()->csrmap.erase(CSR_TIME);
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}
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sim->set_debug(cospike_debug);
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sim->set_histogram(true);
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sim->set_procs_debug(cospike_debug);
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COSPIKE_PRINTF("Setting up htif for spike cosim\n");
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((htif_t*)sim)->start();
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COSPIKE_PRINTF("Spike cosim started\n");
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tohost_addr = ((htif_t*)sim)->get_tohost_addr();
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fromhost_addr = ((htif_t*)sim)->get_fromhost_addr();
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COSPIKE_PRINTF("Tohost : %lx\n", tohost_addr);
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COSPIKE_PRINTF("Fromhost: %lx\n", fromhost_addr);
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COSPIKE_PRINTF("BootROM base : %lx\n", default_boot_rom_addr);
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COSPIKE_PRINTF("BootROM size : %lx\n", boot_rom->contents().size());
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COSPIKE_PRINTF("Memory base : %lx\n", info->mem0_base);
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COSPIKE_PRINTF("Memory size : %lx\n", info->mem0_size);
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}
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if (priv & 0x4) { // debug
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return;
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}
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if (cospike_timeout && cycle > cospike_timeout) {
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if (sim) {
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COSPIKE_PRINTF("Cospike reached timeout cycles = %ld, terminating\n", cospike_timeout);
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delete sim;
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}
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exit(0);
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}
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processor_t* p = sim->get_core(hartid);
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state_t* s = p->get_state();
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#ifdef COSPIKE_DTM
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if (dtm && dtm->loadarch_done && !spike_loadarch_done) {
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COSPIKE_PRINTF("Restoring spike state from testchip_dtm loadarch\n");
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// copy the loadarch state into the cosim
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loadarch_state_t &ls = dtm->loadarch_state[hartid];
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s->pc = ls.pc;
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s->prv = ls.prv;
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s->csrmap[CSR_MSTATUS]->write(s->csrmap[CSR_MSTATUS]->read() | MSTATUS_VS | MSTATUS_XS | MSTATUS_FS);
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#define RESTORE(CSRID, csr) s->csrmap[CSRID]->write(ls.csr);
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RESTORE(CSR_FCSR , fcsr);
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RESTORE(CSR_VSTART , vstart);
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RESTORE(CSR_VXSAT , vxsat);
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RESTORE(CSR_VXRM , vxrm);
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RESTORE(CSR_VCSR , vcsr);
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RESTORE(CSR_VTYPE , vtype);
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RESTORE(CSR_STVEC , stvec);
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RESTORE(CSR_SSCRATCH , sscratch);
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RESTORE(CSR_SEPC , sepc);
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RESTORE(CSR_SCAUSE , scause);
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RESTORE(CSR_STVAL , stval);
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RESTORE(CSR_SATP , satp);
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RESTORE(CSR_MSTATUS , mstatus);
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RESTORE(CSR_MEDELEG , medeleg);
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RESTORE(CSR_MIDELEG , mideleg);
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RESTORE(CSR_MIE , mie);
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RESTORE(CSR_MTVEC , mtvec);
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RESTORE(CSR_MSCRATCH , mscratch);
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RESTORE(CSR_MEPC , mepc);
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RESTORE(CSR_MCAUSE , mcause);
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RESTORE(CSR_MTVAL , mtval);
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RESTORE(CSR_MIP , mip);
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RESTORE(CSR_MCYCLE , mcycle);
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RESTORE(CSR_MINSTRET , minstret);
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if (ls.VLEN != p->VU.VLEN) {
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COSPIKE_PRINTF("VLEN mismatch loadarch: $d != spike: $d\n", ls.VLEN, p->VU.VLEN);
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abort();
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}
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if (ls.ELEN != p->VU.ELEN) {
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COSPIKE_PRINTF("ELEN mismatch loadarch: $d != spike: $d\n", ls.ELEN, p->VU.ELEN);
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abort();
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}
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for (size_t i = 0; i < 32; i++) {
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s->XPR.write(i, ls.XPR[i]);
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s->FPR.write(i, { (uint64_t)ls.FPR[i], (uint64_t)-1 });
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memcpy(p->VU.reg_file + i * ls.VLEN / 8, ls.VPR[i], ls.VLEN / 8);
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}
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spike_loadarch_done = true;
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p->clear_waiting_for_interrupt();
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}
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#endif
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uint64_t s_pc = s->pc;
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uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF;
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bool ssip_interrupt = interrupt_cause == 0x1;
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bool msip_interrupt = interrupt_cause == 0x3;
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bool stip_interrupt = interrupt_cause == 0x5;
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bool mtip_interrupt = interrupt_cause == 0x7;
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bool debug_interrupt = interrupt_cause == 0xe;
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if (raise_interrupt) {
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COSPIKE_PRINTF("%d interrupt %lx\n", cycle, cause);
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if (ssip_interrupt || stip_interrupt) {
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// do nothing
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} else if (msip_interrupt) {
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s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP);
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} else if (mtip_interrupt) {
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s->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP);
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} else if (debug_interrupt) {
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return;
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} else {
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COSPIKE_PRINTF("Unknown interrupt %lx\n", interrupt_cause);
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abort();
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}
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}
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if (raise_exception)
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COSPIKE_PRINTF("%d exception %lx\n", cycle, cause);
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if (valid) {
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p->clear_waiting_for_interrupt();
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COSPIKE_PRINTF("%d Cosim: %lx", cycle, iaddr);
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// if (has_wdata) {
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// COSPIKE_PRINTF(" s: %lx", wdata);
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// }
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COSPIKE_PRINTF("\n");
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}
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if (valid || raise_interrupt || raise_exception) {
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p->clear_waiting_for_interrupt();
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for (auto& e : read_override_devices) e.get()->was_read_from = false;
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p->step(1);
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if (unlikely(cospike_debug)) {
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COSPIKE_PRINTF("spike pc is %lx\n", s->pc);
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COSPIKE_PRINTF("spike mstatus is %lx\n", s->mstatus->read());
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COSPIKE_PRINTF("spike mip is %lx\n", s->mip->read());
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COSPIKE_PRINTF("spike mie is %lx\n", s->mie->read());
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COSPIKE_PRINTF("spike wfi state is %d\n", p->is_waiting_for_interrupt());
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}
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}
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if (valid && !raise_exception) {
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if (s_pc != iaddr) {
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COSPIKE_PRINTF("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr);
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if (unlikely(cospike_debug)) {
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COSPIKE_PRINTF("spike mstatus is %lx\n", s->mstatus->read());
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COSPIKE_PRINTF("spike mcause is %lx\n", s->mcause->read());
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COSPIKE_PRINTF("spike mtval is %lx\n" , s->mtval->read());
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COSPIKE_PRINTF("spike mtinst is %lx\n", s->mtinst->read());
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}
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exit(1);
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}
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auto& mem_write = s->log_mem_write;
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auto& log = s->log_reg_write;
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auto& mem_read = s->log_mem_read;
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for (auto memwrite : mem_write) {
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reg_t waddr = std::get<0>(memwrite);
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uint64_t w_data = std::get<1>(memwrite);
|
||||
if ((waddr == CLINT_BASE + 4*hartid) && w_data == 0) {
|
||||
s->mip->backdoor_write_with_mask(MIP_MSIP, 0);
|
||||
}
|
||||
if ((waddr == CLINT_BASE + 0x4000 + 4*hartid)) {
|
||||
s->mip->backdoor_write_with_mask(MIP_MTIP, 0);
|
||||
}
|
||||
// Try to remember magic_mem addrs, and ignore these in the future
|
||||
if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) {
|
||||
COSPIKE_PRINTF("Probable magic mem %lx\n", w_data);
|
||||
magic_addrs.insert(w_data);
|
||||
}
|
||||
}
|
||||
|
||||
bool scalar_wb = false;
|
||||
bool vector_wb = false;
|
||||
uint32_t vector_cnt = 0;
|
||||
std::vector<reg_t> vector_rds;
|
||||
|
||||
for (auto ®write : log) {
|
||||
|
||||
//TODO: scaling to multi issue reads?
|
||||
reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]);
|
||||
|
||||
int rd = regwrite.first >> 4;
|
||||
int type = regwrite.first & 0xf;
|
||||
|
||||
// 0 => int
|
||||
// 1 => fp
|
||||
// 2 => vec
|
||||
// 3 => vec hint
|
||||
// 4 => csr
|
||||
bool device_read = false;
|
||||
for (auto& e : read_override_devices) if (e.get()->was_read_from) device_read = true;
|
||||
|
||||
bool lr_read = ((insn & MASK_LR_D) == MATCH_LR_D) || ((insn & MASK_LR_W) == MATCH_LR_W);
|
||||
bool sc_read = ((insn & MASK_SC_D) == MATCH_SC_D) || ((insn & MASK_SC_W) == MATCH_SC_W);
|
||||
|
||||
bool ignore_read = sc_read || (!mem_read.empty() &&
|
||||
(magic_addrs.count(mem_read_addr) ||
|
||||
device_read ||
|
||||
lr_read ||
|
||||
(tohost_addr && mem_read_addr == tohost_addr) ||
|
||||
(fromhost_addr && mem_read_addr == fromhost_addr)));
|
||||
//COSPIKE_PRINTF("register write type %d\n", type);
|
||||
// check the type is compliant with writeback first
|
||||
if ((type == 0 || type == 1))
|
||||
scalar_wb = true;
|
||||
if (type == 2) {
|
||||
vector_rds.push_back(rd);
|
||||
vector_wb = true;
|
||||
}
|
||||
if (type == 3) continue;
|
||||
|
||||
if ((rd != 0 && type == 0) || type == 1) {
|
||||
// Override reads from some CSRs
|
||||
uint64_t csr_addr = (insn >> 20) & 0xfff;
|
||||
bool csr_read = (insn & 0x7f) == 0x73;
|
||||
if (csr_read)
|
||||
COSPIKE_PRINTF("CSR read %lx\n", csr_addr);
|
||||
if (csr_read && ((csr_addr == 0x301) || // misa
|
||||
(csr_addr == 0x306) || // mcounteren
|
||||
(csr_addr == 0xf13) || // mimpid
|
||||
(csr_addr == 0xf12) || // marchid
|
||||
(csr_addr == 0xf11) || // mvendorid
|
||||
(csr_addr == 0xb00) || // mcycle
|
||||
(csr_addr == 0xb02) || // minstret
|
||||
(csr_addr == 0xc00) || // cycle
|
||||
(csr_addr == 0xc01) || // time
|
||||
(csr_addr == 0xc02) || // instret
|
||||
(csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers
|
||||
(csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr
|
||||
)) {
|
||||
COSPIKE_PRINTF("CSR override\n");
|
||||
s->XPR.write(rd, wdata);
|
||||
} else if (ignore_read) {
|
||||
// Don't check reads from tohost, reads from magic memory, or reads
|
||||
// from clint Technically this could be buggy because log_mem_read
|
||||
// only reports vaddrs, but no software ever should access
|
||||
// tohost/fromhost/clint with vaddrs anyways
|
||||
COSPIKE_PRINTF("Read override %lx = %lx\n", mem_read_addr, wdata);
|
||||
s->XPR.write(rd, wdata);
|
||||
} else if (wdata != regwrite.second.v[0]) {
|
||||
COSPIKE_PRINTF("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd,
|
||||
regwrite.second.v[0], wdata);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
// TODO FIX: Rocketchip TracedInstruction.wdata should be Valid(UInt)
|
||||
// if (scalar_wb ^ has_wdata) {
|
||||
// COSPIKE_PRINTF("Scalar wdata behavior divergence between spike and DUT\n");
|
||||
// exit(-1);
|
||||
// }
|
||||
}
|
||||
for (auto &a : vector_rds) {
|
||||
COSPIKE_PRINTF("vector writeback to v%d\n", a);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,81 +0,0 @@
|
||||
import "DPI-C" function void cospike_set_sysinfo(
|
||||
input string isa,
|
||||
input int vlen,
|
||||
input string priv,
|
||||
input int pmpregions,
|
||||
input longint mem0_base,
|
||||
input longint mem0_size,
|
||||
input int nharts,
|
||||
input string bootrom
|
||||
);
|
||||
|
||||
import "DPI-C" function void cospike_cosim(input longint cycle,
|
||||
input longint hartid,
|
||||
input bit has_wdata,
|
||||
input bit valid,
|
||||
input longint iaddr,
|
||||
input int insn,
|
||||
input bit raise_exception,
|
||||
input bit raise_interrupt,
|
||||
input longint cause,
|
||||
input longint wdata,
|
||||
input int priv
|
||||
);
|
||||
|
||||
|
||||
module SpikeCosim #(
|
||||
parameter ISA,
|
||||
parameter PRIV,
|
||||
parameter VLEN,
|
||||
parameter PMPREGIONS,
|
||||
parameter MEM0_BASE,
|
||||
parameter MEM0_SIZE,
|
||||
parameter NHARTS,
|
||||
parameter BOOTROM) (
|
||||
input clock,
|
||||
input reset,
|
||||
|
||||
input [63:0] cycle,
|
||||
|
||||
input [63:0] hartid,
|
||||
|
||||
input trace_0_valid,
|
||||
input [63:0] trace_0_iaddr,
|
||||
input [31:0] trace_0_insn,
|
||||
input trace_0_exception,
|
||||
input trace_0_interrupt,
|
||||
input [63:0] trace_0_cause,
|
||||
input trace_0_has_wdata,
|
||||
input [63:0] trace_0_wdata,
|
||||
input [2:0] trace_0_priv,
|
||||
|
||||
input trace_1_valid,
|
||||
input [63:0] trace_1_iaddr,
|
||||
input [31:0] trace_1_insn,
|
||||
input trace_1_exception,
|
||||
input trace_1_interrupt,
|
||||
input [63:0] trace_1_cause,
|
||||
input trace_1_has_wdata,
|
||||
input [63:0] trace_1_wdata,
|
||||
input [2:0] trace_1_priv
|
||||
);
|
||||
|
||||
initial begin
|
||||
cospike_set_sysinfo(ISA, VLEN, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
|
||||
end;
|
||||
|
||||
always @(posedge clock) begin
|
||||
if (!reset) begin
|
||||
if (trace_0_valid || trace_0_exception || trace_0_cause) begin
|
||||
cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr,
|
||||
trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause,
|
||||
trace_0_wdata, trace_0_priv);
|
||||
end
|
||||
if (trace_1_valid || trace_1_exception || trace_1_cause) begin
|
||||
cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr,
|
||||
trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause,
|
||||
trace_1_wdata, trace_1_priv);
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule; // CospikeCosim
|
||||
@@ -1,93 +0,0 @@
|
||||
package chipyard
|
||||
|
||||
import chisel3._
|
||||
import chisel3.experimental.{IntParam, StringParam, IO}
|
||||
import chisel3.util._
|
||||
|
||||
import org.chipsalliance.cde.config.{Parameters, Field, Config}
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
import testchipip.TileTraceIO
|
||||
|
||||
case class SpikeCosimConfig(
|
||||
isa: String,
|
||||
vlen: Int,
|
||||
priv: String,
|
||||
pmpregions: Int,
|
||||
mem0_base: BigInt,
|
||||
mem0_size: BigInt,
|
||||
nharts: Int,
|
||||
bootrom: String,
|
||||
has_dtm: Boolean
|
||||
)
|
||||
|
||||
class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map(
|
||||
"ISA" -> StringParam(cfg.isa),
|
||||
"VLEN" -> IntParam(cfg.vlen),
|
||||
"PRIV" -> StringParam(cfg.priv),
|
||||
"PMPREGIONS" -> IntParam(cfg.pmpregions),
|
||||
"MEM0_BASE" -> IntParam(cfg.mem0_base),
|
||||
"MEM0_SIZE" -> IntParam(cfg.mem0_size),
|
||||
"NHARTS" -> IntParam(cfg.nharts),
|
||||
"BOOTROM" -> StringParam(cfg.bootrom)
|
||||
)) with HasBlackBoxResource
|
||||
{
|
||||
addResource("/csrc/cospike.cc")
|
||||
addResource("/vsrc/cospike.v")
|
||||
if (cfg.has_dtm) addResource("/csrc/cospike_dtm.h")
|
||||
val io = IO(new Bundle {
|
||||
val clock = Input(Clock())
|
||||
val reset = Input(Bool())
|
||||
val cycle = Input(UInt(64.W))
|
||||
val hartid = Input(UInt(64.W))
|
||||
val trace = Input(Vec(2, new Bundle {
|
||||
val valid = Bool()
|
||||
val iaddr = UInt(64.W)
|
||||
val insn = UInt(32.W)
|
||||
val exception = Bool()
|
||||
val interrupt = Bool()
|
||||
val cause = UInt(64.W)
|
||||
val has_wdata = Bool()
|
||||
val wdata = UInt(64.W)
|
||||
val priv = UInt(3.W)
|
||||
}))
|
||||
})
|
||||
}
|
||||
|
||||
object SpikeCosim
|
||||
{
|
||||
def apply(trace: TileTraceIO, hartid: Int, cfg: SpikeCosimConfig) = {
|
||||
val cosim = Module(new SpikeCosim(cfg))
|
||||
val cycle = withClockAndReset(trace.clock, trace.reset) {
|
||||
val r = RegInit(0.U(64.W))
|
||||
r := r + 1.U
|
||||
r
|
||||
}
|
||||
cosim.io.clock := trace.clock
|
||||
cosim.io.reset := trace.reset
|
||||
require(trace.numInsns <= 2)
|
||||
cosim.io.cycle := cycle
|
||||
cosim.io.trace.map(t => {
|
||||
t := DontCare
|
||||
t.valid := false.B
|
||||
})
|
||||
cosim.io.hartid := hartid.U
|
||||
for (i <- 0 until trace.numInsns) {
|
||||
val insn = trace.trace.insns(i)
|
||||
cosim.io.trace(i).valid := insn.valid
|
||||
val signed = Wire(SInt(64.W))
|
||||
signed := insn.iaddr.asSInt
|
||||
cosim.io.trace(i).iaddr := signed.asUInt
|
||||
cosim.io.trace(i).insn := insn.insn
|
||||
cosim.io.trace(i).exception := insn.exception
|
||||
cosim.io.trace(i).interrupt := insn.interrupt
|
||||
cosim.io.trace(i).cause := insn.cause
|
||||
cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B
|
||||
cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U)
|
||||
cosim.io.trace(i).priv := insn.priv
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -9,7 +9,7 @@ import chisel3.util.experimental.BoringUtils
|
||||
|
||||
import org.chipsalliance.cde.config.{Field, Config, Parameters}
|
||||
import freechips.rocketchip.diplomacy.{LazyModule}
|
||||
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
|
||||
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug, ExportDebug, DMI}
|
||||
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.tile.{RocketTile}
|
||||
@@ -178,12 +178,26 @@ class WithTracerVBridge extends ComposeHarnessBinder({
|
||||
}
|
||||
})
|
||||
|
||||
class WithDromajoBridge extends ComposeHarnessBinder({
|
||||
(system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) =>
|
||||
ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil
|
||||
class WithCospikeBridge extends ComposeHarnessBinder({
|
||||
(system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => {
|
||||
implicit val p = chipyard.iobinders.GetSystemParameters(system)
|
||||
val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
|
||||
val tiles = chipyardSystem.tiles
|
||||
val cfg = SpikeCosimConfig(
|
||||
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
|
||||
vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
|
||||
priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
|
||||
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
|
||||
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
|
||||
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
|
||||
nharts = tiles.size,
|
||||
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
|
||||
has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
|
||||
)
|
||||
ports.map { p => p.traces.zipWithIndex.map(t => CospikeBridge(t._1, t._2, cfg)) }
|
||||
}
|
||||
})
|
||||
|
||||
|
||||
class WithTraceGenBridge extends OverrideHarnessBinder({
|
||||
(system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) =>
|
||||
ports.map { p => GroundTestBridge(th.harnessBinderClock, p)(system.p) }; Nil
|
||||
|
||||
Submodule generators/testchipip updated: c80ec1cd79...fcbed9cbc4
Reference in New Issue
Block a user