Fix syntax error in vlsi/Makefile

2019-11-20 19:44:58 -08:00
parent 9a2b19122f
commit a5988c3963
1 changed files with 1 additions and 1 deletions
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -33,7 +33,7 @@ INPUT_CONFS        ?= example.yml
 HAMMER_EXEC        ?= ./example-vlsi
 VLSI_TOP           ?= $(TOP)
 VLSI_OBJ_DIR       ?= $(vlsi_dir)/build
-ifneq($(CUSTOM_VLOG), )
+ifneq ($(CUSTOM_VLOG), )
 	OBJ_DIR        ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
 else
 	OBJ_DIR        ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)