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TinyRocketConfig thru par. sim runs, but gl-sim times out.

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This commit is contained in:
Harrison Liew
2021-06-06 20:19:42 -07:00
parent 81b57f96bd
commit a7214e671c
7 changed files with 106 additions and 83 deletions
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26
vlsi/Makefile
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@@ -26,21 +26,21 @@ SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
ifeq ($(tech_name),asap7)
MACROCOMPILER_MODE ?= --mode synflops
else ifdef USE_SRAM_COMPILER
ifdef USE_SRAM_COMPILER
MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
else
MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
endif
ENV_YML ?= $(vlsi_dir)/env.yml
INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\
INPUT_CONFS ?= example-tools.yml \
$(if $(filter $(tech_name),nangate45),\
example-nangate45.yml,\
example-asap7.yml)
HAMMER_EXEC ?= ./example-vlsi
VLSI_TOP ?= $(TOP)
VLSI_HARNESS_DUT_NAME ?= chiptop
# If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
@@ -100,6 +100,19 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
# simulation input configuration
#########################################################################################
include $(base_dir)/vcs.mk
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
@@ -157,6 +170,9 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
@@ -192,7 +208,7 @@ endif
SYN_CONF = $(OBJ_DIR)/inputs.yml
GENERATED_CONFS = $(SYN_CONF)
ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
GENERATED_CONFS += $(SRAM_CONF)
endif
$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)

153
vlsi/example-asap7.yml
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@@ -2,7 +2,8 @@
# Technology used is ASAP7
vlsi.core.technology: asap7
# Specify dir with ASAP7 tarball
technology.asap7.tarball_dir: ""
#technology.asap7.tarball_dir: ""
technology.asap7.tarball_dir: "/tools/B/asap7"
vlsi.core.max_threads: 12
@@ -40,39 +41,72 @@ par.generate_power_straps_options:
track_spacing: 0
track_spacing_M3: 1 # to avoid M2 shorts at higher density
track_start: 10
power_utilization: 0.05
power_utilization: 0.2
power_utilization_M8: 1.0
power_utilization_M9: 1.0
# Placement Constraints
# For ASAP7, all numbers must be 4x larger than final GDS
vlsi.inputs.placement_constraints:
- path: "Sha3AccelwBB"
- path: "ChipTop"
type: toplevel
x: 0
y: 0
width: 300
height: 300
width: 800
height: 500
margins:
left: 0
right: 0
top: 0
bottom: 0
- path: "Sha3AccelwBB/dco"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 550
y: 25
orientation: "r0"
top_layer: "M4"
master: "SRAM1RW4096x8"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
type: hardmacro
x: 550
y: 270
orientation: "r0"
top_layer: "M4"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
type: hardmacro
x: 675
y: 25
orientation: "r0"
top_layer: "M4"
master: "SRAM1RW4096x8"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
type: hardmacro
x: 675
y: 270
orientation: "r0"
top_layer: "M4"
master: "SRAM1RW4096x8"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
type: hardmacro
x: 125
y: 150
orientation: "my"
top_layer: "M4"
master: "SRAM1RW64x21"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 108
y: 108
width: 128
height: 128
orientation: r0
top_layer: M9
- path: "Sha3AccelwBB/place_obs_bottom"
type: obstruction
obs_types: ["place"]
x: 0
y: 0
width: 300
height: 1.08 # 1 core site tall, necessary to avoid shorts
y: 25
orientation: "my"
top_layer: "M4"
master: "SRAM1RW1024x32"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
type: hardmacro
x: 0
y: 260
orientation: "my"
top_layer: "M4"
master: "SRAM1RW1024x37"
# Pin placement constraints
vlsi.inputs.pin_mode: generated
@@ -81,64 +115,37 @@ vlsi.inputs.pin.assignments: [
{pins: "*", layers: ["M5", "M7"], side: "bottom"}
]
# Paths to extra libraries
vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
vlsi.technology.extra_libraries:
- library:
nldm liberty file_deepsubst_meta: "local"
nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
lef file_deepsubst_meta: "local"
lef file: "extra_libraries/example/ExampleDCO.lef"
gds file_deepsubst_meta: "local"
gds file: "extra_libraries/example/ExampleDCO.gds"
corner:
nmos: "slow"
pmos: "slow"
temperature: "100 C"
supplies:
VDD: "0.63 V"
GND: "0 V"
- library:
nldm liberty file_deepsubst_meta: "local"
nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
lef file_deepsubst_meta: "local"
lef file: "extra_libraries/example/ExampleDCO.lef"
gds file_deepsubst_meta: "local"
gds file: "extra_libraries/example/ExampleDCO.gds"
corner:
nmos: "fast"
pmos: "fast"
temperature: "0 C"
supplies:
VDD: "0.77 V"
GND: "0 V"
# Because the DCO is a dummy layout, we treat it as a physical-only cell
par.inputs.physical_only_cells_mode: append
par.inputs.physical_only_cells_list:
- ExampleDCO
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/asap7"]
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
# Genus options
vlsi.core.synthesis_tool: "genus"
vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
synthesis.genus.version: "1813"
# Innovus options
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "181"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options
vlsi.core.drc_tool: "calibre"
vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
vlsi.core.lvs_tool: "calibre"
vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
# VCS options
#vlsi.core.sim_tool: "vcs"
#vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
#vlsi.core.sim_tool_path_meta: "append"
#sim.vcs.version: "P-2019.06"
## Genus options
#vlsi.core.synthesis_tool: "genus"
#vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
#vlsi.core.synthesis_tool_path_meta: "append"
#synthesis.genus.version: "1813"
## Innovus options
#vlsi.core.par_tool: "innovus"
#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
#vlsi.core.par_tool_path_meta: "append"
#par.innovus.version: "191"
#par.innovus.design_flow_effort: "standard"
#par.inputs.gds_merge: true
## Voltus options
#vlsi.core.power_tool: "voltus"
#vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
#vlsi.core.power_tool_path_meta: "append"
#power.voltus.version: "191"
## Calibre options
#vlsi.core.drc_tool: "calibre"
#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
#vlsi.core.lvs_tool: "calibre"
#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]

2
vlsi/example-tools.yml
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@@ -26,7 +26,7 @@ vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
vlsi.core.sim_tool: "vcs"
vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
sim.vcs.version: "P-2019.06-SP2-5"
# # Voltus options
# Voltus options
vlsi.core.power_tool: "voltus"
vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
vlsi.core.power_tool_path_meta: "append"

2
vlsi/hammer

Submodule vlsi/hammer updated: 8fd1486499...353af21da3

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: 3e5b046be1...81e9a97f84

2
vlsi/hammer-synopsys-plugins

Submodule vlsi/hammer-synopsys-plugins updated: f8a7922220...5825e6dc4b

2
vlsi/sim.mk
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@@ -31,7 +31,7 @@ redo-sim-par-$(VLSI_TOP): $(SIM_CONF)
redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
redo-sim-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
redo-sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir
redo-sim-par-$(VLSI_TOP: override HAMMER_SIM_RUN_DIR = sim-par-$(VLSI_TOP)
redo-sim-par-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-par-$(VLSI_TOP)
redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par
redo-sim-par-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) redo-sim-par-$(VLSI_TOP)
redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)