TinyRocketConfig thru par. sim runs, but gl-sim times out.
This commit is contained in:
Harrison Liew
@@ -2,7 +2,8 @@
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# Technology used is ASAP7
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vlsi.core.technology: asap7
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# Specify dir with ASAP7 tarball
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technology.asap7.tarball_dir: ""
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#technology.asap7.tarball_dir: ""
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technology.asap7.tarball_dir: "/tools/B/asap7"
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vlsi.core.max_threads: 12
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@@ -40,39 +41,72 @@ par.generate_power_straps_options:
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track_spacing: 0
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track_spacing_M3: 1 # to avoid M2 shorts at higher density
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track_start: 10
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power_utilization: 0.05
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power_utilization: 0.2
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power_utilization_M8: 1.0
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power_utilization_M9: 1.0
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# Placement Constraints
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# For ASAP7, all numbers must be 4x larger than final GDS
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vlsi.inputs.placement_constraints:
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- path: "Sha3AccelwBB"
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 300
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height: 300
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width: 800
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height: 500
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margins:
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left: 0
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right: 0
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top: 0
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bottom: 0
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- path: "Sha3AccelwBB/dco"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
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type: hardmacro
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x: 550
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y: 25
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orientation: "r0"
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top_layer: "M4"
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master: "SRAM1RW4096x8"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
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type: hardmacro
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x: 550
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y: 270
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orientation: "r0"
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top_layer: "M4"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
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type: hardmacro
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x: 675
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y: 25
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orientation: "r0"
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top_layer: "M4"
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master: "SRAM1RW4096x8"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
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type: hardmacro
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x: 675
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y: 270
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orientation: "r0"
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top_layer: "M4"
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master: "SRAM1RW4096x8"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
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type: hardmacro
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x: 125
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y: 150
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orientation: "my"
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top_layer: "M4"
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master: "SRAM1RW64x21"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 108
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y: 108
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width: 128
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height: 128
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orientation: r0
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top_layer: M9
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- path: "Sha3AccelwBB/place_obs_bottom"
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type: obstruction
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obs_types: ["place"]
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x: 0
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y: 0
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width: 300
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height: 1.08 # 1 core site tall, necessary to avoid shorts
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y: 25
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orientation: "my"
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top_layer: "M4"
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master: "SRAM1RW1024x32"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
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type: hardmacro
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x: 0
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y: 260
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orientation: "my"
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top_layer: "M4"
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master: "SRAM1RW1024x37"
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# Pin placement constraints
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vlsi.inputs.pin_mode: generated
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@@ -81,64 +115,37 @@ vlsi.inputs.pin.assignments: [
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{pins: "*", layers: ["M5", "M7"], side: "bottom"}
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]
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# Paths to extra libraries
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vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
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vlsi.technology.extra_libraries:
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- library:
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nldm liberty file_deepsubst_meta: "local"
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nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
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lef file_deepsubst_meta: "local"
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lef file: "extra_libraries/example/ExampleDCO.lef"
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gds file_deepsubst_meta: "local"
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gds file: "extra_libraries/example/ExampleDCO.gds"
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corner:
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nmos: "slow"
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pmos: "slow"
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temperature: "100 C"
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supplies:
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VDD: "0.63 V"
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GND: "0 V"
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- library:
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nldm liberty file_deepsubst_meta: "local"
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nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
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lef file_deepsubst_meta: "local"
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lef file: "extra_libraries/example/ExampleDCO.lef"
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gds file_deepsubst_meta: "local"
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gds file: "extra_libraries/example/ExampleDCO.gds"
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corner:
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nmos: "fast"
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pmos: "fast"
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temperature: "0 C"
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supplies:
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VDD: "0.77 V"
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GND: "0 V"
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# Because the DCO is a dummy layout, we treat it as a physical-only cell
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par.inputs.physical_only_cells_mode: append
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par.inputs.physical_only_cells_list:
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- ExampleDCO
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# SRAM Compiler compiler options
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vlsi.core.sram_generator_tool: "sram_compiler"
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# You should specify a location for the SRAM generator in the tech plugin
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vlsi.core.sram_generator_tool_path: []
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vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/asap7"]
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vlsi.core.sram_generator_tool_path_meta: "append"
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# Tool options. Replace with your tool plugin of choice.
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# Genus options
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vlsi.core.synthesis_tool: "genus"
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vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
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vlsi.core.synthesis_tool_path_meta: "append"
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synthesis.genus.version: "1813"
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# Innovus options
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vlsi.core.par_tool: "innovus"
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vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
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vlsi.core.par_tool_path_meta: "append"
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par.innovus.version: "181"
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par.innovus.design_flow_effort: "standard"
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par.inputs.gds_merge: true
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# Calibre options
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vlsi.core.drc_tool: "calibre"
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vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
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vlsi.core.lvs_tool: "calibre"
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vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
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# VCS options
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#vlsi.core.sim_tool: "vcs"
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#vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
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#vlsi.core.sim_tool_path_meta: "append"
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#sim.vcs.version: "P-2019.06"
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## Genus options
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#vlsi.core.synthesis_tool: "genus"
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#vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
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#vlsi.core.synthesis_tool_path_meta: "append"
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#synthesis.genus.version: "1813"
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## Innovus options
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#vlsi.core.par_tool: "innovus"
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#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
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#vlsi.core.par_tool_path_meta: "append"
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#par.innovus.version: "191"
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#par.innovus.design_flow_effort: "standard"
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#par.inputs.gds_merge: true
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## Voltus options
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#vlsi.core.power_tool: "voltus"
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#vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
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#vlsi.core.power_tool_path_meta: "append"
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#power.voltus.version: "191"
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## Calibre options
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#vlsi.core.drc_tool: "calibre"
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#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
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#vlsi.core.lvs_tool: "calibre"
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#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
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