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Merge pull request #1369 from ucb-bar/sim-syn-par-fix

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This commit is contained in:
Harrison Liew
2023-03-10 15:09:58 -08:00
committed by GitHub
parent a98a3163a8 0883993000
commit a8c9c8271e
2 changed files with 9 additions and 3 deletions
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10
vlsi/Makefile
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@@ -46,9 +46,9 @@ VLSI_MODEL_DUT_NAME ?= chiptop
# If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
else
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP)
endif
#########################################################################################
@@ -118,6 +118,12 @@ endif
$(SYN_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " input_files:" >> $@
for x in $$(cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@

2
vlsi/sim.mk
View File

@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $$(cat $(sim_common_files)); do \
for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@