wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Use SV48 when possible

Browse Source
This commit is contained in:
abejgonzalez
2024-04-12 15:38:23 -07:00
parent 766ea735ac
commit aaab8b4265
2 changed files with 8 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
generators/chipyard/src/main/scala/config/AbstractConfig.scala
View File

@@ -120,6 +120,7 @@ class AbstractConfig extends Config(
// Bus/interconnect settings
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */
// ================================================
@@ -134,7 +135,7 @@ class AbstractConfig extends Config(
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */

7
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -5,7 +5,7 @@ import chisel3._
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, PgLevels}
import cva6.{CVA6TileAttachParams}
import sodor.common.{SodorTileAttachParams}
@@ -126,3 +126,8 @@ class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams]
))
}
})
// Uses SV48 if possible, otherwise default to the Rocket Chip core default
class WithSV48IfPossible extends Config((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
})