improved example-designs override
This commit is contained in:
Nayiri K
@@ -1,152 +1,7 @@
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# Override configurations in ../example-sky130.yml
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# Specify clock signals
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# Relax the clock period for OpenROAD to meet timing
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vlsi.inputs.clocks: [
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{name: "clock_clock", period: "10ns", uncertainty: "1ns"}
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{name: "clock_clock", period: "30ns", uncertainty: "1ns"}
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]
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# # Power Straps
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# par.power_straps_mode: generate
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# par.generate_power_straps_method: by_tracks
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# par.blockage_spacing: 40.0
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# par.blockage_spacing_top_layer: met4
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# par.generate_power_straps_options:
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# by_tracks:
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# strap_layers:
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# - met4
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# - met5
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# pin_layers:
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# - met5
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# blockage_spacing_met2: 4.0
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# blockage_spacing_met4: 2.0
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# blockage_spacing_met4: 2.0
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# track_width: 3
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# track_width_met5: 1
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# track_spacing: 5
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# track_start: 10
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# track_start_met5: 1
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# power_utilization: 0.1
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# power_utilization_met4: 0.1
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# power_utilization_met5: 0.1
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 3500
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height: 2500
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margins:
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left: 10
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right: 10
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top: 10
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bottom: 10
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# # Place data cache SRAM instances
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
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# type: hardmacro
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# x: 50
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# y: 100
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
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# type: hardmacro
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# x: 50
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# y: 700
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
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# type: hardmacro
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# x: 50
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# y: 1300
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
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# type: hardmacro
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# x: 50
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# y: 1900
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
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# type: hardmacro
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# x: 1000
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# y: 1900
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
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# type: hardmacro
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# x: 1000
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# y: 1300
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
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# type: hardmacro
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# x: 1000
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# y: 700
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
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# type: hardmacro
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# x: 1000
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# y: 100
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# orientation: r0
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# # Place instruction cache SRAM instances
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
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# type: hardmacro
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# x: 3250
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# y: 100
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
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# type: hardmacro
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# x: 3250
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# y: 700
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# orientation: r0
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
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# type: hardmacro
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# x: 3450
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# y: 1300
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# orientation: r0
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# Place L2 TLB SRAM instances
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# for some reason these don't remain SRAMs in the Yosys synthesis
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_0"
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# type: hardmacro
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# x: 2000
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# y: 1300
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# orientation: "r0"
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_1"
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# type: hardmacro
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# x: 2000
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# y: 1900
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# orientation: "r0"
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_2"
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# type: hardmacro
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# x: 2750
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# y: 1300
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# orientation: "r0"
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_3"
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# type: hardmacro
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# x: 2750
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# y: 1900
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# orientation: "r0"
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# - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_4"
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# type: hardmacro
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# x: 3460
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# y: 1900
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# orientation: "r0"
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# # Override pin placement constraints
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# vlsi.inputs.pin_mode: generated
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# vlsi.inputs.pin.generate_mode: semi_auto
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# vlsi.inputs.pin.assignments: [
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# {pins: "*", layers: ["met2", "met4"], side: "bottom"}
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# ]
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@@ -5,32 +5,32 @@ tutorial ?= none
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# TODO: eventually have asap7 commercial/openroad tutorial flavors
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ifeq ($(tutorial),asap7)
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tech_name ?= asap7
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-tools.yml
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TECH_CONF ?= example-asap7.yml
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INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF)
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VLSI_OBJ_DIR ?= build-asap7-commercial
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tech_name ?= asap7
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-tools.yml
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TECH_CONF ?= example-asap7.yml
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INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF)
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VLSI_OBJ_DIR ?= build-asap7-commercial
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endif
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ifeq ($(tutorial),sky130-commercial)
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tech_name ?= sky130
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-tools.yml
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TECH_CONF ?= example-sky130.yml
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DESIGN_CONF ?= example-designs/sky130-commercial.yml
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EXTRA_CONFS ?= $(if $(filter $(TOP),Rocket RocketTile), example-designs/sky130-rocket.yml, )
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
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VLSI_OBJ_DIR ?= build-sky130-commercial
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tech_name ?= sky130
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-tools.yml
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TECH_CONF ?= example-sky130.yml
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DESIGN_CONF ?= example-designs/sky130-commercial.yml
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EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
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VLSI_OBJ_DIR ?= build-sky130-commercial
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endif
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ifeq ($(tutorial),sky130-openroad)
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tech_name ?= sky130
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-openroad.yml
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TECH_CONF ?= example-sky130.yml
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DESIGN_CONF ?= example-designs/sky130-openroad.yml
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EXTRA_CONFS ?= $(if $(filter $(TOP),Rocket RocketTile), example-designs/sky130-rocket.yml, )
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
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VLSI_OBJ_DIR ?= build-sky130-openroad
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tech_name ?= sky130
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-openroad.yml
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TECH_CONF ?= example-sky130.yml
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DESIGN_CONF ?= example-designs/sky130-openroad.yml
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EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
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VLSI_OBJ_DIR ?= build-sky130-openroad
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endif
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