Fix Arty100T Verilog build (#1608)

* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs

.github/scripts/defaults.sh

@@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
-grouping["group-fpga"]="arty vcu118 vc707"
+grouping["group-fpga"]="arty vcu118 vc707 arty100t"
 
 # key value store to get the build strings
 declare -A mapping
@@ -81,3 +81,4 @@ mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig
 mapping["arty"]="SUB_PROJECT=arty verilog"
 mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
 mapping["vc707"]="SUB_PROJECT=vc707 verilog"
+mapping["arty100t"]="SUB_PROJECT=arty100t verilog"

fpga/src/main/scala/arty100t/Harness.scala

@@ -54,6 +54,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
   override lazy val module = new HarnessLikeImpl
 
   class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
+    all_leds.foreach(_ := DontCare)
     clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
 
     val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock