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vlsi changes

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This commit is contained in:
Richard Yan
2024-09-22 01:15:38 -07:00
parent 1e85033a33
commit ae427a8a2d
3 changed files with 7 additions and 5 deletions
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9
vlsi/Makefile
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@@ -19,7 +19,7 @@ include $(base_dir)/variables.mk
# vlsi types and rules # vlsi types and rules
######################################################################################### #########################################################################################
sim_name ?= vcs # needed for GenerateSimFiles, but is unused sim_name ?= vcs # needed for GenerateSimFiles, but is unused
tech_name ?= asap7 tech_name ?= intech22
tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\ tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
$(shell python3 -c "import os, hammer.technology.$(tech_name);\ $(shell python3 -c "import os, hammer.technology.$(tech_name);\
print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\ print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\
@@ -35,9 +35,9 @@ else
endif endif
ENV_YML ?= $(vlsi_dir)/env.yml ENV_YML ?= $(vlsi_dir)/env.yml
TECH_CONF ?= example-$(tech_name).yml TECH_CONF ?= $(tech_name).yml
TOOLS_CONF ?= example-tools.yml TOOLS_CONF ?= example-tools.yml
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) example-design.yml
HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
./example-vlsi-sky130,\ ./example-vlsi-sky130,\
./example-vlsi) ./example-vlsi)
@@ -86,8 +86,9 @@ else
ifneq ($(EXT_FILELISTS),) ifneq ($(EXT_FILELISTS),)
cat $(EXT_FILELISTS) >> $(VLSI_RTL) cat $(EXT_FILELISTS) >> $(VLSI_RTL)
endif endif
./make_syn_f.sh $(build_dir)
endif endif
$(vlsi_dir)/make_syn_f.sh $(build_dir)
######################################################################################### #########################################################################################
# srams # srams

1
vlsi/add.mems.conf
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@@ -3,3 +3,4 @@ name dcache_tags depth 16 width 24 ports write,read
name cache_mshr depth 8 width 305 ports write,read name cache_mshr depth 8 width 305 ports write,read
name icache_data depth 128 width 1024 ports mwrite,read mask_gran 8 name icache_data depth 128 width 1024 ports mwrite,read mask_gran 8
name icache_tags depth 128 width 21 ports write,read name icache_tags depth 128 width 21 ports write,read
name rf_bank depth 64 width 32 ports write,read

2
vlsi/sim.mk
View File

@@ -13,7 +13,7 @@ $(SIM_CONF): $(sim_common_files) check-binary
echo " tb_name: ''" >> $@ # don't specify -top echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@ echo " input_files:" >> $@
# plusarg_reader is bugged, TODO perhaps raise the issue again in chipyard #1388 and #1442 # plusarg_reader is bugged, TODO perhaps raise the issue again in chipyard #1388 and #1442
for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(GEN_COLLATERAL_DIR)/GenericDeserializer.sv $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " input_files_meta: 'append'" >> $@ echo " input_files_meta: 'append'" >> $@