vlsi changes
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@@ -19,7 +19,7 @@ include $(base_dir)/variables.mk
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# vlsi types and rules
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#########################################################################################
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sim_name ?= vcs # needed for GenerateSimFiles, but is unused
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tech_name ?= asap7
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tech_name ?= intech22
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tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
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$(shell python3 -c "import os, hammer.technology.$(tech_name);\
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print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\
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@@ -35,9 +35,9 @@ else
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endif
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ENV_YML ?= $(vlsi_dir)/env.yml
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TECH_CONF ?= example-$(tech_name).yml
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TECH_CONF ?= $(tech_name).yml
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TOOLS_CONF ?= example-tools.yml
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF)
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) example-design.yml
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HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
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./example-vlsi-sky130,\
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./example-vlsi)
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@@ -86,8 +86,9 @@ else
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ifneq ($(EXT_FILELISTS),)
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cat $(EXT_FILELISTS) >> $(VLSI_RTL)
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endif
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./make_syn_f.sh $(build_dir)
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endif
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$(vlsi_dir)/make_syn_f.sh $(build_dir)
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#########################################################################################
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# srams
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@@ -3,3 +3,4 @@ name dcache_tags depth 16 width 24 ports write,read
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name cache_mshr depth 8 width 305 ports write,read
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name icache_data depth 128 width 1024 ports mwrite,read mask_gran 8
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name icache_tags depth 128 width 21 ports write,read
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name rf_bank depth 64 width 32 ports write,read
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@@ -13,7 +13,7 @@ $(SIM_CONF): $(sim_common_files) check-binary
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echo " tb_name: ''" >> $@ # don't specify -top
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echo " input_files:" >> $@
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# plusarg_reader is bugged, TODO perhaps raise the issue again in chipyard #1388 and #1442
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for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(GEN_COLLATERAL_DIR)/GenericDeserializer.sv $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
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for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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