Remove extra spaces in FPGA makefile

2022-03-02 15:45:27 +01:00
parent 481398b910
commit af78c9cadf
1 changed files with 1 additions and 1 deletions
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -118,7 +118,7 @@ $(BIT_FILE): $(synth_list_f)
 		-tclargs \
 			-top-module "$(MODEL)" \
 			-F "$(synth_list_f)" \
-			-board "$(BOARD)" \			
+			-board "$(BOARD)" \
 			-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')"

 .PHONY: bitstream