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Remove extra spaces in FPGA makefile

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This commit is contained in:
Abraham Gonzalez
2022-03-02 15:45:27 +01:00
committed by GitHub
parent 481398b910
commit af78c9cadf
1 changed files with 1 additions and 1 deletions
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fpga/Makefile
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@@ -118,7 +118,7 @@ $(BIT_FILE): $(synth_list_f)
-tclargs \ -tclargs \
-top-module "$(MODEL)" \ -top-module "$(MODEL)" \
-F "$(synth_list_f)" \ -F "$(synth_list_f)" \
-board "$(BOARD)" \ -board "$(BOARD)" \
-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')"
.PHONY: bitstream .PHONY: bitstream