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Fix ICache SPAD base addr to avoid conflicts with default SerialTL mem

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This commit is contained in:
Jerry Zhao
2021-01-10 23:38:11 -08:00
parent 6d8627f36d
commit b1b230ba01
1 changed files with 1 additions and 1 deletions
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generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -141,7 +141,7 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
class WithRocketICacheScratchpad extends Config((site, here, up) => { class WithRocketICacheScratchpad extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site) map { r => case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000)))) r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000))))
} }
}) })