Merge pull request #1832 from ucb-bar/ext-verilog

EXT_FILELISTS and EXT_INCDIR APIs for including external verilog projects

common.mk

@@ -310,8 +310,13 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_S
 # note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated,
 #       however it is really unneeded since ALL_MODS_FILELIST includes all BB files
 ########################################################################################
-$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST)
-	sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
+$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) $(EXT_FILELISTS)
+ifneq (,$(EXT_FILELISTS))
+	cat $(EXT_FILELISTS) > $@
+else
+	rm -f $@
+endif
+	sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' >> $@
 	echo "$(TOP_SMEMS_FILE)" >> $@
 	echo "$(MODEL_SMEMS_FILE)" >> $@
 

scripts/insert-includes.py

@@ -34,13 +34,15 @@ def process(inF, outF):
             # for each include found, search through all dirs and replace if found, error if not
             for num, line in enumerate(inFile, 1):
                 match = re.match(r"^ *`include +\"(.*)\"", line)
-                if match:
+                if match and match.group(1) != "uvm_macros.svh":
+                    print("[INFO] Replacing includes for {}".format(match.group(1)))
                     # search for include and replace
                     found = False
                     for d in incDirs:
                         potentialIncFileName = d + "/" + match.group(1)
                         if os.path.exists(potentialIncFileName):
                             found = True
+                            print("[INFO] Found missing include in {}".format(potentialIncFileName))
                             with open(potentialIncFileName, 'r') as incFile:
                                 for iline in incFile:
                                     outFile.write(iline)

sims/vcs/vcs.mk

@@ -51,7 +51,9 @@ VCS_NONCC_OPTS = \
 	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
-	+incdir+$(GEN_COLLATERAL_DIR)
+	-top $(TB) \
+	+incdir+$(GEN_COLLATERAL_DIR) \
+	$(addprefix +incdir+,$(EXT_INCDIRS))
 
 VCS_PREPROC_DEFINES = \
 	+define+VCS

sims/verilator/Makefile

@@ -154,6 +154,7 @@ VERILATOR_NONCC_OPTS = \
 	$(VERILATOR_PREPROC_DEFINES) \
 	--top-module $(TB) \
 	--vpi \
+	$(addprefix +incdir+,$(EXT_INCDIRS)) \
 	-f $(sim_common_files)
 
 #----------------------------------------------------------------------------------------

variables.mk

@@ -213,6 +213,12 @@ BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f
 # all module files to include (top, model, bb included)
 ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f
 
+# external filelists. Users, or project-supplied make fragments can append filelists
+# with absolute paths here
+EXT_FILELISTS ?=
+# external verilog incdirs. Users, or project-supplied make fragments can append to this
+EXT_INCDIRS ?=
+
 BOOTROM_FILES   ?= bootrom.rv64.img bootrom.rv32.img
 BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
 

vlsi/Makefile

@@ -72,7 +72,7 @@ VLSI_RTL = $(build_dir)/syn.f
 ifneq ($(CUSTOM_VLOG), )
 	RTL_DEPS = $(CUSTOM_VLOG)
 else
-	RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE)
+	RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) $(EXT_FILELISTS)
 endif
 
 $(VLSI_RTL): $(RTL_DEPS)
@@ -82,6 +82,9 @@ ifneq ($(CUSTOM_VLOG), )
 else
 	cat $(TOP_MODS_FILELIST) | sort -u > $(VLSI_RTL)
 	echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
+ifneq ($(EXT_FILELISTS),)
+	cat $(EXT_FILELISTS) >> $(VLSI_RTL)
+endif
 endif
 
 #########################################################################################