Merge pull request #682 from ucb-bar/clocking-features

Add tile-reset control registers | multiclock fixes

generators/chipyard/src/main/scala/Clocks.scala

@@ -5,12 +5,13 @@ import chisel3._
 import scala.collection.mutable.{ArrayBuffer}
 
 import freechips.rocketchip.prci._
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
+import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, InstantiatesTiles}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule}
 import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider}
 
 import barstools.iocell.chisel._
+import testchipip.{TLTileResetCtrl}
 
 import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
 
@@ -109,9 +110,20 @@ object ClockingSchemeGenerators {
         l.asyncClockGroupsNode
     }
 
+    // Add a control register for each tile's reset
+    val resetSetter = chiptop.lazySystem match {
+      case sys: BaseSubsystem with InstantiatesTiles => TLTileResetCtrl(sys)
+      case _ => ClockGroupEphemeralNode()
+    }
+
     val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
-    chiptop.implicitClockSinkNode := ClockGroup() := aggregator
+    (chiptop.implicitClockSinkNode
-    systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator
+      := ClockGroup()
+      := aggregator)
+    (systemAsyncClockGroup
+      := resetSetter
+      := ClockGroupNamePrefixer()
+      := aggregator)
 
     val referenceClockSource =  ClockSourceNode(Seq(ClockSourceParameters()))
     (aggregator

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -117,6 +117,7 @@ class LoopbackNICRocketConfig extends Config(
 
 // DOC include start: l1scratchpadrocket
 class ScratchpadOnlyRocketConfig extends Config(
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp}
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart._
 
@@ -67,9 +67,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 
 class WithSerialBridge extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
-    ports.map { p =>
+    ports.map { port =>
-      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset)
+      implicit val p = GetSystemParameters(system)
-      SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system))
+      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
+      SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
     }
     Nil
   }