Merge pull request #669 from ucb-bar/local-fpga-arty-abe
Misc Additions to Local FPGA Branch
This commit is contained in:
Abraham Gonzalez
3
fpga/.gitignore
vendored
Normal file
3
fpga/.gitignore
vendored
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@@ -0,0 +1,3 @@
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*
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!.gitignore
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!Makefile
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92
fpga/Makefile
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92
fpga/Makefile
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@@ -0,0 +1,92 @@
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#########################################################################################
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# fpga prototype makefile
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#########################################################################################
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#########################################################################################
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# general path variables
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#########################################################################################
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base_dir=$(abspath ..)
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sim_dir=$(abspath .)
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# do not generate simulation files
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sim_name := none
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#########################################################################################
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# include shared variables
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#########################################################################################
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include $(base_dir)/variables.mk
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# default variables to build the arty example
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SUB_PROJECT := fpga
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SBT_PROJECT := freedomPlatforms
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MODEL := E300ArtyDevKitFPGAChip
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VLOG_MODEL := E300ArtyDevKitFPGAChip
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MODEL_PACKAGE := chipyard.fpga
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CONFIG := E300ArtyDevKitConfig
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CONFIG_PACKAGE := chipyard.fpga
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GENERATOR_PACKAGE := chipyard
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TB := none # unused
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TOP := E300ArtyDevKitPlatform
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# setup the board to use
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BOARD ?= arty
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.PHONY: default
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default: $(mcs)
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#########################################################################################
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# misc. directories
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#########################################################################################
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fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx
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fpga_common_script_dir := $(fpga_dir)/common/tcl
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#########################################################################################
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# import other necessary rules and variables
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#########################################################################################
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include $(base_dir)/common.mk
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#########################################################################################
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# copy from other directory
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#########################################################################################
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all_vsrcs := \
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$(sim_vsrcs) \
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$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
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$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
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#########################################################################################
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# vivado rules
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#########################################################################################
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# combine all sources into single .f
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synth_list_f := $(build_dir)/$(long_name).vsrcs.f
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$(synth_list_f): $(sim_common_files) $(all_vsrcs)
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$(foreach file,$(all_vsrcs),echo "$(file)" >> $@;)
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cat $(sim_common_files) >> $@
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BIT_FILE := $(build_dir)/obj/$(MODEL).bit
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$(BIT_FILE): $(synth_list_f)
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cd $(build_dir); vivado \
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-nojournal -mode batch \
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-source $(fpga_common_script_dir)/vivado.tcl \
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-tclargs \
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-top-module "$(MODEL)" \
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-F "$(synth_list_f)" \
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-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \
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-board "$(BOARD)"
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.PHONY: bit
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bit: $(BIT_FILE)
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# Build .mcs
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MCS_FILE := $(build_dir)/obj/$(MODEL).mcs
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$(MCS_FILE): $(BIT_FILE)
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cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
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.PHONY: mcs
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mcs: $(MCS_FILE)
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#########################################################################################
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# general cleanup rules
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#########################################################################################
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.PHONY: clean
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clean:
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rm -rf $(gen_dir)
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@@ -1,23 +0,0 @@
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# See LICENSE for license details.
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base_dir=$(abspath ..)
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BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit
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FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx
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MODEL := E300ArtyDevKitFPGAChip
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PROJECT := sifive.freedom.everywhere.e300artydevkit
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export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
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export CONFIG := E300ArtyDevKitConfig
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export BOARD := arty
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export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip
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rocketchip_dir := $(base_dir)/generators/rocket-chip
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sifiveblocks_dir := $(base_dir)/generators/sifive-blocks
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VSRCS := \
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$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
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$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
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$(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \
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$(sifiveblocks_dir)/vsrc/SRLatch.v \
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$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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include common.mk
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@@ -1,45 +0,0 @@
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# RISCV environment variable must be set
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CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
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OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
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CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
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LFLAGS=-static -nostdlib
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dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
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$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
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dtc -I dts -O dtb -o $@ $<
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.PHONY: dtb
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dtb: $(dtb)
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elf := $(BUILD_DIR)/xip.elf
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$(elf): xip.S $(dtb)
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$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
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.PHONY: elf
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elf: $(elf)
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bin := $(BUILD_DIR)/xip.bin
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$(bin): $(elf)
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$(OBJCOPY) -O binary $< $@
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.PHONY: bin
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bin: $(bin)
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hex := $(BUILD_DIR)/xip.hex
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$(hex): $(bin)
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od -t x4 -An -w4 -v $< > $@
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.PHONY: hex
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hex: $(hex)
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romgen := $(BUILD_DIR)/rom.v
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$(romgen): $(hex)
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$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
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.PHONY: romgen
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romgen: $(romgen)
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.PHONY: clean
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clean::
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rm -rf $(hex) $(elf)
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@@ -1,16 +0,0 @@
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// See LICENSE for license details.
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// Execute in place
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// Jump directly to XIP_TARGET_ADDR
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.section .text.init
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.option norvc
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.globl _start
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_start:
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csrr a0, mhartid
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la a1, dtb
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li t0, XIP_TARGET_ADDR
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jr t0
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.section .rodata
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dtb:
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.incbin DEVICE_TREE
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119
fpga/common.mk
119
fpga/common.mk
@@ -1,119 +0,0 @@
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# See LICENSE for license details.
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# Required variables:
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# - MODEL
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# - PROJECT
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# - CONFIG_PROJECT
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# - CONFIG
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# - BUILD_DIR
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# - FPGA_DIR
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# Optional variables:
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# - EXTRA_FPGA_VSRCS
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# export to bootloader
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export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
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# export to fpga-shells
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export FPGA_TOP_SYSTEM=$(MODEL)
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export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
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export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
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export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
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export BUILD_DIR
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EXTRA_FPGA_VSRCS ?=
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PATCHVERILOG ?= ""
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BOOTROM_DIR ?= ""
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base_dir=$(abspath ..)
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export rocketchip_dir := $(base_dir)/generators/rocket-chip
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SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10
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SBT_PROJECT ?= chipyard
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firrtl_dir := $(base_dir)/tools/firrtl
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# Build firrtl.jar and put it where chisel3 can find it.
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FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
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FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
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$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala")
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$(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala
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mkdir -p $(base_dir)/lib
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cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR)
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# Build .fir
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long_name := $(CONFIG_PROJECT).$(CONFIG)
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firrtl := $(BUILD_DIR)/$(long_name).fir
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$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "project freedomPlatforms" \
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"runMain chipyard.Generator \
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--target-dir $(BUILD_DIR) \
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--name $(long_name) \
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--top-module $(PROJECT).$(MODEL) \
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--legacy-configs $(CONFIG_PROJECT).$(CONFIG)"
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.PHONY: firrtl
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firrtl: $(firrtl)
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# Build .v
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verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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$(verilog): $(firrtl) $(FIRRTL_JAR)
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$(FIRRTL) -i $(firrtl) -o $@ -X verilog
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ifneq ($(PATCHVERILOG),"")
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$(PATCHVERILOG)
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endif
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.PHONY: verilog
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verilog: $(verilog)
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romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
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$(romgen): $(verilog)
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ifneq ($(BOOTROM_DIR),"")
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$(MAKE) -C $(BOOTROM_DIR) romgen
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mv $(BUILD_DIR)/rom.v $@
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endif
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.PHONY: romgen
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romgen: $(romgen)
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f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
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$(f):
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echo $(VSRCS) > $@
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bit := $(BUILD_DIR)/obj/$(MODEL).bit
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$(bit): $(romgen) $(f)
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cd $(BUILD_DIR); vivado \
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-nojournal -mode batch \
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-source $(fpga_common_script_dir)/vivado.tcl \
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-tclargs \
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-top-module "$(MODEL)" \
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-F "$(f)" \
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-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
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-board "$(BOARD)"
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# Build .mcs
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mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
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$(mcs): $(bit)
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cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
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||||
.PHONY: mcs
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||||
mcs: $(mcs)
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||||
|
||||
# Build Libero project
|
||||
prjx := $(BUILD_DIR)/libero/$(MODEL).prjx
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$(prjx): $(verilog)
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||||
cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)"
|
||||
|
||||
.PHONY: prjx
|
||||
prjx: $(prjx)
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||||
|
||||
# Clean
|
||||
.PHONY: clean
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||||
clean:
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||||
ifneq ($(BOOTROM_DIR),"")
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||||
$(MAKE) -C $(BOOTROM_DIR) clean
|
||||
endif
|
||||
$(MAKE) -C $(FPGA_DIR) clean
|
||||
rm -rf $(BUILD_DIR)
|
||||
@@ -1,5 +1,5 @@
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// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
package chipyard.fpga
|
||||
|
||||
import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
|
||||
@@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._
|
||||
import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.i2c._
|
||||
|
||||
// Default FreedomEConfig
|
||||
class DefaultFreedomEConfig extends Config (
|
||||
new WithNBreakpoints(2) ++
|
||||
new WithNExtTopInterrupts(0) ++
|
||||
new WithJtagDTM ++
|
||||
new TinyConfig
|
||||
)
|
||||
|
||||
// Freedom E300 Arty Dev Kit Peripherals
|
||||
class E300DevKitPeripherals extends Config((site, here, up) => {
|
||||
class E300DevKitExtra extends Config((site, here, up) => {
|
||||
case PeripheryGPIOKey => List(
|
||||
GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
|
||||
case PeripheryPWMKey => List(
|
||||
@@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => {
|
||||
I2CParams(address = 0x10016000))
|
||||
case PeripheryMockAONKey =>
|
||||
MockAONParams(address = 0x10000000)
|
||||
case PeripheryMaskROMKey => List(
|
||||
MaskROMParams(address = 0x10000, name = "BootROM"))
|
||||
case DTSTimebase => BigInt(32768)
|
||||
case JtagDTMKey => new JtagDTMConfig (
|
||||
idcodeVersion = 2,
|
||||
idcodePartNum = 0x000,
|
||||
idcodeManufId = 0x489,
|
||||
debugIdleCycles = 5)
|
||||
})
|
||||
|
||||
// Freedom E300 Arty Dev Kit Peripherals
|
||||
class E300ArtyDevKitConfig extends Config(
|
||||
new E300DevKitPeripherals ++
|
||||
new DefaultFreedomEConfig().alter((site,here,up) => {
|
||||
case DTSTimebase => BigInt(32768)
|
||||
case JtagDTMKey => new JtagDTMConfig (
|
||||
idcodeVersion = 2,
|
||||
idcodePartNum = 0x000,
|
||||
idcodeManufId = 0x489,
|
||||
debugIdleCycles = 5)
|
||||
})
|
||||
)
|
||||
new E300DevKitExtra ++
|
||||
new chipyard.config.WithBootROM ++
|
||||
new chipyard.config.WithL2TLBs(1024) ++
|
||||
new freechips.rocketchip.subsystem.With1TinyCore ++
|
||||
new freechips.rocketchip.subsystem.WithNBanks(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNoMemPort ++
|
||||
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
|
||||
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
|
||||
new freechips.rocketchip.subsystem.WithJtagDTM ++
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
|
||||
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
package chipyard.fpga
|
||||
|
||||
import Chisel._
|
||||
import chisel3.core.{attach}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
package chipyard.fpga
|
||||
|
||||
import Chisel._
|
||||
|
||||
@@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.i2c._
|
||||
import sifive.blocks.devices.pinctrl._
|
||||
|
||||
import chipyard.{DigitalTop}
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// PinGen
|
||||
//-------------------------------------------------------------------------
|
||||
@@ -51,7 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
|
||||
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
|
||||
val sys = Module(LazyModule(new DigitalTop).module)
|
||||
val io = new E300ArtyDevKitPlatformIO
|
||||
|
||||
// This needs to be de-asserted synchronously to the coreClk.
|
||||
|
||||
@@ -1,51 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
|
||||
import Chisel._
|
||||
|
||||
import freechips.rocketchip.config._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.devices.debug._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.system._
|
||||
|
||||
import sifive.blocks.devices.mockaon._
|
||||
import sifive.blocks.devices.gpio._
|
||||
import sifive.blocks.devices.pwm._
|
||||
import sifive.blocks.devices.spi._
|
||||
import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.i2c._
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// E300ArtyDevKitSystem
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
|
||||
with HasPeripheryDebug
|
||||
with HasPeripheryMockAON
|
||||
with chipyard.example.CanHavePeripheryGCD
|
||||
with HasPeripheryUART
|
||||
with HasPeripherySPIFlash
|
||||
with HasPeripherySPI
|
||||
with HasPeripheryGPIO
|
||||
with HasPeripheryPWM
|
||||
with HasPeripheryI2C {
|
||||
override lazy val module = new E300ArtyDevKitSystemModule(this)
|
||||
}
|
||||
|
||||
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
|
||||
extends RocketSubsystemModuleImp(_outer)
|
||||
with HasPeripheryDebugModuleImp
|
||||
with chipyard.example.CanHavePeripheryGCDModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripherySPIModuleImp
|
||||
with HasPeripheryGPIOModuleImp
|
||||
with HasPeripherySPIFlashModuleImp
|
||||
with HasPeripheryMockAONModuleImp
|
||||
with HasPeripheryPWMModuleImp
|
||||
with HasPeripheryI2CModuleImp {
|
||||
// Reset vector is set to the location of the mask rom
|
||||
val maskROMParams = p(PeripheryMaskROMKey)
|
||||
global_reset_vector := maskROMParams(0).address.U
|
||||
}
|
||||
@@ -13,6 +13,10 @@ import freechips.rocketchip.devices.tilelink._
|
||||
|
||||
// DOC include start: DigitalTop
|
||||
class DigitalTop(implicit p: Parameters) extends ChipyardSystem
|
||||
with sifive.blocks.devices.mockaon.HasPeripheryMockAON
|
||||
with sifive.blocks.devices.spi.HasPeripherySPI
|
||||
with sifive.blocks.devices.pwm.HasPeripheryPWM
|
||||
with sifive.blocks.devices.i2c.HasPeripheryI2C
|
||||
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
|
||||
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
|
||||
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
|
||||
@@ -31,6 +35,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
|
||||
}
|
||||
|
||||
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
|
||||
with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp
|
||||
with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
|
||||
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
|
||||
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
|
||||
with testchipip.CanHaveTraceIOModuleImp
|
||||
with testchipip.CanHavePeripheryBlockDeviceModuleImp
|
||||
with testchipip.CanHavePeripherySerialModuleImp
|
||||
|
||||
@@ -11,6 +11,7 @@ case class GenerateSimConfig(
|
||||
sealed trait Simulator
|
||||
object VerilatorSimulator extends Simulator
|
||||
object VCSSimulator extends Simulator
|
||||
object NotSimulator extends Simulator
|
||||
|
||||
trait HasGenerateSimConfig {
|
||||
val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
|
||||
@@ -22,15 +23,16 @@ trait HasGenerateSimConfig {
|
||||
.action((x, c) => x match {
|
||||
case "verilator" => c.copy(simulator = VerilatorSimulator)
|
||||
case "vcs" => c.copy(simulator = VCSSimulator)
|
||||
case "none" => c.copy(simulator = NotSimulator)
|
||||
case _ => throw new Exception(s"Unrecognized simulator $x")
|
||||
})
|
||||
.text("Name of simulator to generate files for (verilator, vcs)")
|
||||
.text("Name of simulator to generate files for (verilator, vcs, none)")
|
||||
|
||||
opt[String]("target-dir")
|
||||
.abbr("td")
|
||||
.valueName("<target-directory>")
|
||||
.action((x, c) => c.copy(targetDir = x))
|
||||
.text("Target director to put files")
|
||||
.text("Target directory to put files")
|
||||
|
||||
opt[String]("dotFName")
|
||||
.abbr("df")
|
||||
@@ -50,6 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
|
||||
case VerilatorSimulator => s"-FI ${fname}"
|
||||
// vcs pulls headers in with +incdir, doesn't have anything like verilator.h
|
||||
case VCSSimulator => ""
|
||||
case _ => ""
|
||||
}
|
||||
} else { // do nothing otherwise
|
||||
fname
|
||||
@@ -82,26 +85,31 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
|
||||
out.close()
|
||||
}
|
||||
def resources(sim: Simulator): Seq[String] = Seq(
|
||||
"/testchipip/csrc/SimSerial.cc",
|
||||
"/testchipip/csrc/SimDRAM.cc",
|
||||
"/testchipip/csrc/mm.h",
|
||||
"/testchipip/csrc/mm.cc",
|
||||
"/testchipip/csrc/mm_dramsim2.h",
|
||||
"/testchipip/csrc/mm_dramsim2.cc",
|
||||
"/csrc/SimDTM.cc",
|
||||
"/csrc/SimJTAG.cc",
|
||||
"/csrc/remote_bitbang.h",
|
||||
"/csrc/remote_bitbang.cc",
|
||||
"/vsrc/EICG_wrapper.v",
|
||||
) ++ (sim match { // simulator specific files to include
|
||||
case VerilatorSimulator => Seq(
|
||||
"/csrc/emulator.cc",
|
||||
"/csrc/verilator.h",
|
||||
)
|
||||
case VCSSimulator => Seq(
|
||||
"/vsrc/TestDriver.v",
|
||||
)
|
||||
})
|
||||
) ++ (sim match {
|
||||
case NotSimulator => Seq()
|
||||
case _ => Seq(
|
||||
"/testchipip/csrc/SimSerial.cc",
|
||||
"/testchipip/csrc/SimDRAM.cc",
|
||||
"/testchipip/csrc/mm.h",
|
||||
"/testchipip/csrc/mm.cc",
|
||||
"/testchipip/csrc/mm_dramsim2.h",
|
||||
"/testchipip/csrc/mm_dramsim2.cc",
|
||||
"/csrc/SimDTM.cc",
|
||||
"/csrc/SimJTAG.cc",
|
||||
"/csrc/remote_bitbang.h",
|
||||
"/csrc/remote_bitbang.cc",
|
||||
)
|
||||
}) ++ (sim match { // simulator specific files to include
|
||||
case VerilatorSimulator => Seq(
|
||||
"/csrc/emulator.cc",
|
||||
"/csrc/verilator.h",
|
||||
)
|
||||
case VCSSimulator => Seq(
|
||||
"/vsrc/TestDriver.v",
|
||||
)
|
||||
case _ => Seq()
|
||||
})
|
||||
|
||||
def writeBootrom(): Unit = {
|
||||
firrtl.FileUtils.makeDirectory("./bootrom/")
|
||||
|
||||
Reference in New Issue
Block a user