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Merge pull request #669 from ucb-bar/local-fpga-arty-abe

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Misc Additions to Local FPGA Branch
This commit is contained in:
Abraham Gonzalez
2020-09-06 21:00:57 -07:00
committed by GitHub
parent 3b6d584672 1fa1b6d57f
commit b6a54ead59
12 changed files with 160 additions and 302 deletions
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3
fpga/.gitignore vendored Normal file
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@@ -0,0 +1,3 @@
*
!.gitignore
!Makefile

92
fpga/Makefile Normal file
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@@ -0,0 +1,92 @@
#########################################################################################
# fpga prototype makefile
#########################################################################################
#########################################################################################
# general path variables
#########################################################################################
base_dir=$(abspath ..)
sim_dir=$(abspath .)
# do not generate simulation files
sim_name := none
#########################################################################################
# include shared variables
#########################################################################################
include $(base_dir)/variables.mk
# default variables to build the arty example
SUB_PROJECT := fpga
SBT_PROJECT := freedomPlatforms
MODEL := E300ArtyDevKitFPGAChip
VLOG_MODEL := E300ArtyDevKitFPGAChip
MODEL_PACKAGE := chipyard.fpga
CONFIG := E300ArtyDevKitConfig
CONFIG_PACKAGE := chipyard.fpga
GENERATOR_PACKAGE := chipyard
TB := none # unused
TOP := E300ArtyDevKitPlatform
# setup the board to use
BOARD ?= arty
.PHONY: default
default: $(mcs)
#########################################################################################
# misc. directories
#########################################################################################
fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx
fpga_common_script_dir := $(fpga_dir)/common/tcl
#########################################################################################
# import other necessary rules and variables
#########################################################################################
include $(base_dir)/common.mk
#########################################################################################
# copy from other directory
#########################################################################################
all_vsrcs := \
$(sim_vsrcs) \
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
#########################################################################################
# vivado rules
#########################################################################################
# combine all sources into single .f
synth_list_f := $(build_dir)/$(long_name).vsrcs.f
$(synth_list_f): $(sim_common_files) $(all_vsrcs)
$(foreach file,$(all_vsrcs),echo "$(file)" >> $@;)
cat $(sim_common_files) >> $@
BIT_FILE := $(build_dir)/obj/$(MODEL).bit
$(BIT_FILE): $(synth_list_f)
cd $(build_dir); vivado \
-nojournal -mode batch \
-source $(fpga_common_script_dir)/vivado.tcl \
-tclargs \
-top-module "$(MODEL)" \
-F "$(synth_list_f)" \
-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \
-board "$(BOARD)"
.PHONY: bit
bit: $(BIT_FILE)
# Build .mcs
MCS_FILE := $(build_dir)/obj/$(MODEL).mcs
$(MCS_FILE): $(BIT_FILE)
cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
.PHONY: mcs
mcs: $(MCS_FILE)
#########################################################################################
# general cleanup rules
#########################################################################################
.PHONY: clean
clean:
rm -rf $(gen_dir)

23
fpga/Makefile.e300artydevkit
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@@ -1,23 +0,0 @@
# See LICENSE for license details.
base_dir=$(abspath ..)
BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit
FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx
MODEL := E300ArtyDevKitFPGAChip
PROJECT := sifive.freedom.everywhere.e300artydevkit
export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
export CONFIG := E300ArtyDevKitConfig
export BOARD := arty
export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip
rocketchip_dir := $(base_dir)/generators/rocket-chip
sifiveblocks_dir := $(base_dir)/generators/sifive-blocks
VSRCS := \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
include common.mk

45
fpga/bootrom/xip/Makefile
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@@ -1,45 +0,0 @@
# RISCV environment variable must be set
CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
LFLAGS=-static -nostdlib
dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
dtc -I dts -O dtb -o $@ $<
.PHONY: dtb
dtb: $(dtb)
elf := $(BUILD_DIR)/xip.elf
$(elf): xip.S $(dtb)
$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
.PHONY: elf
elf: $(elf)
bin := $(BUILD_DIR)/xip.bin
$(bin): $(elf)
$(OBJCOPY) -O binary $< $@
.PHONY: bin
bin: $(bin)
hex := $(BUILD_DIR)/xip.hex
$(hex): $(bin)
od -t x4 -An -w4 -v $< > $@
.PHONY: hex
hex: $(hex)
romgen := $(BUILD_DIR)/rom.v
$(romgen): $(hex)
$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
.PHONY: romgen
romgen: $(romgen)
.PHONY: clean
clean::
rm -rf $(hex) $(elf)

16
fpga/bootrom/xip/xip.S
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@@ -1,16 +0,0 @@
// See LICENSE for license details.
// Execute in place
// Jump directly to XIP_TARGET_ADDR
.section .text.init
.option norvc
.globl _start
_start:
csrr a0, mhartid
la a1, dtb
li t0, XIP_TARGET_ADDR
jr t0
.section .rodata
dtb:
.incbin DEVICE_TREE

119
fpga/common.mk
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@@ -1,119 +0,0 @@
# See LICENSE for license details.
# Required variables:
# - MODEL
# - PROJECT
# - CONFIG_PROJECT
# - CONFIG
# - BUILD_DIR
# - FPGA_DIR
# Optional variables:
# - EXTRA_FPGA_VSRCS
# export to bootloader
export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
# export to fpga-shells
export FPGA_TOP_SYSTEM=$(MODEL)
export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
export BUILD_DIR
EXTRA_FPGA_VSRCS ?=
PATCHVERILOG ?= ""
BOOTROM_DIR ?= ""
base_dir=$(abspath ..)
export rocketchip_dir := $(base_dir)/generators/rocket-chip
SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10
SBT_PROJECT ?= chipyard
firrtl_dir := $(base_dir)/tools/firrtl
# Build firrtl.jar and put it where chisel3 can find it.
FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala")
$(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala
mkdir -p $(base_dir)/lib
cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR)
# Build .fir
long_name := $(CONFIG_PROJECT).$(CONFIG)
firrtl := $(BUILD_DIR)/$(long_name).fir
$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "project freedomPlatforms" \
"runMain chipyard.Generator \
--target-dir $(BUILD_DIR) \
--name $(long_name) \
--top-module $(PROJECT).$(MODEL) \
--legacy-configs $(CONFIG_PROJECT).$(CONFIG)"
.PHONY: firrtl
firrtl: $(firrtl)
# Build .v
verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
$(verilog): $(firrtl) $(FIRRTL_JAR)
$(FIRRTL) -i $(firrtl) -o $@ -X verilog
ifneq ($(PATCHVERILOG),"")
$(PATCHVERILOG)
endif
.PHONY: verilog
verilog: $(verilog)
romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
$(romgen): $(verilog)
ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) romgen
mv $(BUILD_DIR)/rom.v $@
endif
.PHONY: romgen
romgen: $(romgen)
f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
$(f):
echo $(VSRCS) > $@
bit := $(BUILD_DIR)/obj/$(MODEL).bit
$(bit): $(romgen) $(f)
cd $(BUILD_DIR); vivado \
-nojournal -mode batch \
-source $(fpga_common_script_dir)/vivado.tcl \
-tclargs \
-top-module "$(MODEL)" \
-F "$(f)" \
-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
-board "$(BOARD)"
# Build .mcs
mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
$(mcs): $(bit)
cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
.PHONY: mcs
mcs: $(mcs)
# Build Libero project
prjx := $(BUILD_DIR)/libero/$(MODEL).prjx
$(prjx): $(verilog)
cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)"
.PHONY: prjx
prjx: $(prjx)
# Clean
.PHONY: clean
clean:
ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) clean
endif
$(MAKE) -C $(FPGA_DIR) clean
rm -rf $(BUILD_DIR)

41
fpga/src/main/scala/arty/Config.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit package chipyard.fpga
import freechips.rocketchip.config._ import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
@@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._ import sifive.blocks.devices.i2c._
// Default FreedomEConfig class E300DevKitExtra extends Config((site, here, up) => {
class DefaultFreedomEConfig extends Config (
new WithNBreakpoints(2) ++
new WithNExtTopInterrupts(0) ++
new WithJtagDTM ++
new TinyConfig
)
// Freedom E300 Arty Dev Kit Peripherals
class E300DevKitPeripherals extends Config((site, here, up) => {
case PeripheryGPIOKey => List( case PeripheryGPIOKey => List(
GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
case PeripheryPWMKey => List( case PeripheryPWMKey => List(
@@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => {
I2CParams(address = 0x10016000)) I2CParams(address = 0x10016000))
case PeripheryMockAONKey => case PeripheryMockAONKey =>
MockAONParams(address = 0x10000000) MockAONParams(address = 0x10000000)
case PeripheryMaskROMKey => List(
MaskROMParams(address = 0x10000, name = "BootROM"))
})
// Freedom E300 Arty Dev Kit Peripherals
class E300ArtyDevKitConfig extends Config(
new E300DevKitPeripherals ++
new DefaultFreedomEConfig().alter((site,here,up) => {
case DTSTimebase => BigInt(32768) case DTSTimebase => BigInt(32768)
case JtagDTMKey => new JtagDTMConfig ( case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, idcodeVersion = 2,
idcodePartNum = 0x000, idcodePartNum = 0x000,
idcodeManufId = 0x489, idcodeManufId = 0x489,
debugIdleCycles = 5) debugIdleCycles = 5)
}) })
)
class E300ArtyDevKitConfig extends Config(
new E300DevKitExtra ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.With1TinyCore ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithJtagDTM ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

2
fpga/src/main/scala/arty/FPGAChip.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit package chipyard.fpga
import Chisel._ import Chisel._
import chisel3.core.{attach} import chisel3.core.{attach}

6
fpga/src/main/scala/arty/Platform.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit package chipyard.fpga
import Chisel._ import Chisel._
@@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._ import sifive.blocks.devices.i2c._
import sifive.blocks.devices.pinctrl._ import sifive.blocks.devices.pinctrl._
import chipyard.{DigitalTop}
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
// PinGen // PinGen
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
@@ -51,7 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) val sys = Module(LazyModule(new DigitalTop).module)
val io = new E300ArtyDevKitPlatformIO val io = new E300ArtyDevKitPlatformIO
// This needs to be de-asserted synchronously to the coreClk. // This needs to be de-asserted synchronously to the coreClk.

51
fpga/src/main/scala/arty/System.scala
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@@ -1,51 +0,0 @@
// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.system._
import sifive.blocks.devices.mockaon._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
//-------------------------------------------------------------------------
// E300ArtyDevKitSystem
//-------------------------------------------------------------------------
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
with HasPeripheryDebug
with HasPeripheryMockAON
with chipyard.example.CanHavePeripheryGCD
with HasPeripheryUART
with HasPeripherySPIFlash
with HasPeripherySPI
with HasPeripheryGPIO
with HasPeripheryPWM
with HasPeripheryI2C {
override lazy val module = new E300ArtyDevKitSystemModule(this)
}
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
extends RocketSubsystemModuleImp(_outer)
with HasPeripheryDebugModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with HasPeripheryUARTModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp
with HasPeripherySPIFlashModuleImp
with HasPeripheryMockAONModuleImp
with HasPeripheryPWMModuleImp
with HasPeripheryI2CModuleImp {
// Reset vector is set to the location of the mask rom
val maskROMParams = p(PeripheryMaskROMKey)
global_reset_vector := maskROMParams(0).address.U
}

8
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -13,6 +13,10 @@ import freechips.rocketchip.devices.tilelink._
// DOC include start: DigitalTop // DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with sifive.blocks.devices.mockaon.HasPeripheryMockAON
with sifive.blocks.devices.spi.HasPeripherySPI
with sifive.blocks.devices.pwm.HasPeripheryPWM
with sifive.blocks.devices.i2c.HasPeripheryI2C
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
@@ -31,6 +35,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
} }
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp with testchipip.CanHavePeripherySerialModuleImp

16
generators/utilities/src/main/scala/Simulator.scala
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@@ -11,6 +11,7 @@ case class GenerateSimConfig(
sealed trait Simulator sealed trait Simulator
object VerilatorSimulator extends Simulator object VerilatorSimulator extends Simulator
object VCSSimulator extends Simulator object VCSSimulator extends Simulator
object NotSimulator extends Simulator
trait HasGenerateSimConfig { trait HasGenerateSimConfig {
val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
@@ -22,15 +23,16 @@ trait HasGenerateSimConfig {
.action((x, c) => x match { .action((x, c) => x match {
case "verilator" => c.copy(simulator = VerilatorSimulator) case "verilator" => c.copy(simulator = VerilatorSimulator)
case "vcs" => c.copy(simulator = VCSSimulator) case "vcs" => c.copy(simulator = VCSSimulator)
case "none" => c.copy(simulator = NotSimulator)
case _ => throw new Exception(s"Unrecognized simulator $x") case _ => throw new Exception(s"Unrecognized simulator $x")
}) })
.text("Name of simulator to generate files for (verilator, vcs)") .text("Name of simulator to generate files for (verilator, vcs, none)")
opt[String]("target-dir") opt[String]("target-dir")
.abbr("td") .abbr("td")
.valueName("<target-directory>") .valueName("<target-directory>")
.action((x, c) => c.copy(targetDir = x)) .action((x, c) => c.copy(targetDir = x))
.text("Target director to put files") .text("Target directory to put files")
opt[String]("dotFName") opt[String]("dotFName")
.abbr("df") .abbr("df")
@@ -50,6 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
case VerilatorSimulator => s"-FI ${fname}" case VerilatorSimulator => s"-FI ${fname}"
// vcs pulls headers in with +incdir, doesn't have anything like verilator.h // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
case VCSSimulator => "" case VCSSimulator => ""
case _ => ""
} }
} else { // do nothing otherwise } else { // do nothing otherwise
fname fname
@@ -82,6 +85,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
out.close() out.close()
} }
def resources(sim: Simulator): Seq[String] = Seq( def resources(sim: Simulator): Seq[String] = Seq(
"/vsrc/EICG_wrapper.v",
) ++ (sim match {
case NotSimulator => Seq()
case _ => Seq(
"/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimSerial.cc",
"/testchipip/csrc/SimDRAM.cc", "/testchipip/csrc/SimDRAM.cc",
"/testchipip/csrc/mm.h", "/testchipip/csrc/mm.h",
@@ -92,8 +99,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
"/csrc/SimJTAG.cc", "/csrc/SimJTAG.cc",
"/csrc/remote_bitbang.h", "/csrc/remote_bitbang.h",
"/csrc/remote_bitbang.cc", "/csrc/remote_bitbang.cc",
"/vsrc/EICG_wrapper.v", )
) ++ (sim match { // simulator specific files to include }) ++ (sim match { // simulator specific files to include
case VerilatorSimulator => Seq( case VerilatorSimulator => Seq(
"/csrc/emulator.cc", "/csrc/emulator.cc",
"/csrc/verilator.h", "/csrc/verilator.h",
@@ -101,6 +108,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
case VCSSimulator => Seq( case VCSSimulator => Seq(
"/vsrc/TestDriver.v", "/vsrc/TestDriver.v",
) )
case _ => Seq()
}) })
def writeBootrom(): Unit = { def writeBootrom(): Unit = {