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Update clocking stuff to chisel 3.5.6

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This commit is contained in:
Jerry Zhao
2023-04-08 14:53:09 -07:00
parent 32f0f83900
commit b7b2a62d80
4 changed files with 4 additions and 4 deletions
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2
generators/chipyard/src/main/scala/clocking/FakePLL.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._
// A simple config demonstrating how to set up a basic chip in Chipyard