rename missing vcs/verilator names | fix ci path

docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst

@@ -227,7 +227,7 @@ Now with all of that done, we can go ahead and run our simulation.
 
 .. code-block:: shell
 
-    cd verisim
+    cd verilator
     make CONFIG=PWMConfig
     ./simulator-example-PWMConfig ../tests/pwm.riscv
 

docs/Getting-Started/Chipyard-Basics.rst

@@ -81,14 +81,14 @@ Toolchains
 Sims
 -------------------------------------------
 
-**verisim (Verilator wrapper)**
+**verilator (Verilator wrapper)**
   Verilator is an open source Verilog simulator.
-  The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
+  The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
   See :ref:`Verilator` for more information.
 
-**vsim (VCS wrapper)**
+**vcs (VCS wrapper)**
   VCS is a proprietary Verilog simulator.
-  Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
+  Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
   See :ref:`VCS` for more information.
 
 **FireSim**

docs/Getting-Started/Running-A-Simulation.rst

@@ -15,9 +15,9 @@ The following instructions assume at least one of these simulators is installed.
 Verilator/VCS Flows
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Verilator is an open-source RTL simulator.
-We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
+We run Verilator simulations from within the ``sims/verilator`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
 On the other hand, VCS is a proprietary RTL simulator.
-We run VCS simulations from within the ``sims/vsim`` directory.
+We run VCS simulations from within the ``sims/vcs`` directory.
 Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS.
 
 First, we will start by entering the Verilator or VCS directory:
@@ -25,12 +25,12 @@ First, we will start by entering the Verilator or VCS directory:
 .. code-block:: shell
 
     # Enter Verilator directory
-    cd sims/verisim
+    cd sims/verilator
 
     # OR
 
     # Enter VCS directory
-    cd sims/vsim
+    cd sims/vcs
 
 In order to construct the simulator with our custom design, we run the following command within the simulator directory: